openwrt/target/linux/realtek
Sander Vanheule 396dc89ee7 realtek: correct egress frame port verification
Destination switch ports for outgoing frame can range from 0 to
CPU_PORT-1.

Refactor the code to only generate egress frame CPU headers when a valid
destination port number is available, and make the code a bit more
consistent between different switch generations. Change the dest_port
argument's type to 'unsigned int', since only positive values are valid.

This fixes the issue where egress frames on switch port 0 did not
receive a VLAN tag, because they are sent out without a CPU header.
Also fixes a potential issue with invalid (negative) egress port numbers
on RTL93xx switches.

Reported-by: Arınç ÜNAL <arinc.unal@xeront.com>
Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 1773264a0c)
2022-07-21 20:59:51 +02:00
..
base-files realtek: add ZyXEL GS1900-24HP v1 support 2022-04-19 21:45:46 +02:00
dts-5.10 realtek: rename u-boot-env2 to board-name 2022-07-08 22:09:52 -03:00
files/firmware/rtl838x_phy realtek: update the tree to the latest refactored version 2020-11-26 13:29:27 +01:00
files-5.10 realtek: correct egress frame port verification 2022-07-21 20:59:51 +02:00
image realtek: build sane factory images for DGS-1210 models 2022-07-08 22:10:16 -03:00
patches-5.10 kernel: Refresh patches for all targets 2022-07-03 18:54:04 +02:00
profiles target: use SPDX license identifiers on Makefiles 2021-02-10 15:47:18 +01:00
rtl838x generic: enable CRYPTO_LIB_BLAKE2S[_X86|_ARM] 2022-06-27 22:34:07 +02:00
rtl839x generic: enable CRYPTO_LIB_BLAKE2S[_X86|_ARM] 2022-06-27 22:34:07 +02:00
rtl930x generic: enable CRYPTO_LIB_BLAKE2S[_X86|_ARM] 2022-06-27 22:34:07 +02:00
rtl931x generic: enable CRYPTO_LIB_BLAKE2S[_X86|_ARM] 2022-06-27 22:34:07 +02:00
Makefile realtek: Fix tc default package 2022-03-29 14:28:21 +02:00