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31a6605de0
Serge Vasilugin reports: To improve mt7620 built-in wifi performance some changes: 1. Correct BW20/BW40 switching (see comments with mark (1)) 2. Correct TX_SW_CFG1 MAC reg from v3 of vendor driver see https://gitlab.com/dm38/padavan-ng/-/blob/master/trunk/proprietary/rt_wifi/rtpci/3.0.X.X/mt76x2/chips/rt6352.c#L531 3. Set bbp66 for all chains. 4. US_CYC_CNT init based on Programming guide, default value was 33 (pci), set chipset bus clock with fallback to cpu clock/3. 5. Don't overwrite default values for mt7620. 6. Correct some typos. 7. Add support for external LNA: a) RF and BBP regs never be corrected for this mode b) eLNA is driven the same way as ePA with mt7620's pin PA but vendor driver explicitly pin PA to gpio mode (for forrect calibration?) so I'm not sure that request for pa_pin in dts-file will be enough First 5 changes (really 2) improve performance for boards w/o eLNA/ePA. Changes 7 add support for eLNA Configuration w/o eLAN/ePA and with eLNA show results tx/rx (from router point of view) for each stream: 35-40/30-35 Mbps for HT20 65-70/60-65 Mbps for HT40 Yes. Max results for 2T2R client is 140-145/135-140 with peaks 160/150, It correspond to mediatek driver results. Boards with ePA untested. Reported-by: Serge Vasilugin <vasilugin@yandex.ru> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
191 lines
3.1 KiB
Plaintext
191 lines
3.1 KiB
Plaintext
#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "dlink,dch-m225", "ralink,mt7620a-soc";
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model = "D-Link DCH-M225";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RFKILL>;
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};
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reset {
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label = "reset";
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "green:power";
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gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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status {
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label = "red:status";
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gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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};
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "Audio-I2S";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink0_master>;
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simple-audio-card,frame-master = <&dailink0_master>;
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simple-audio-card,widgets =
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"Headphone", "Headphones";
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simple-audio-card,routing =
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"Headphones", "HP_L",
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"Headphones", "HP_R";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,hp-det-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
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simple-audio-card,cpu {
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sound-dai = <&i2s>;
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};
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dailink0_master: simple-audio-card,codec {
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sound-dai = <&codec>;
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&i2c {
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status = "okay";
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codec: wm8960@1a {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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wlf,shared-lrclk;
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};
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};
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&i2s {
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#sound-dai-cells = <0>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_refclk_pins>;
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <80000000>;
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m25p,fast-read;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x4000>;
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read-only;
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};
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factory: partition@34000 {
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label = "factory";
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reg = <0x34000 0x4000>;
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read-only;
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};
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nvram: partition@38000 {
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label = "nvram";
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reg = <0x38000 0x8000>;
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read-only;
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};
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partition@40000 {
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label = "devconf";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "upgrade_rec";
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reg = <0x50000 0x100000>;
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read-only;
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};
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partition@150000 {
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compatible = "seama";
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label = "firmware";
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reg = <0x150000 0x6b0000>;
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};
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};
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};
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};
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&gdma {
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status = "okay";
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};
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&state_default {
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gpio {
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groups = "wdt", "rgmii1";
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function = "gpio";
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};
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gpio_i2s {
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groups = "uartf";
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function = "gpio i2s";
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};
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};
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ðernet {
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nvmem-cells = <&macaddr_factory_4>;
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nvmem-cell-names = "mac-address";
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0x0>;
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pinctrl-names = "default", "pa_gpio";
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pinctrl-0 = <&pa_pins>;
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pinctrl-1 = <&pa_gpio_pins>;
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};
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&factory {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_4: macaddr@4 {
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reg = <0x4 0x6>;
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};
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};
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