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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
153 lines
4.4 KiB
Diff
153 lines
4.4 KiB
Diff
From aa43601d97bf9136b657259f44c03a6a30b70d07 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 26 Dec 2019 11:35:58 +0100
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Subject: [PATCH] drm/vc4: crtc: Add BCM2711 pixelvalves
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The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add
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support for them.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 82 +++++++++++++++++++++++++++++++++-
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drivers/gpu/drm/vc4/vc4_regs.h | 6 +++
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2 files changed, 86 insertions(+), 2 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -273,6 +273,13 @@ static u32 vc4_get_fifo_full_level(struc
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case PV_CONTROL_FORMAT_24:
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case PV_CONTROL_FORMAT_DSIV_24:
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default:
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+ /*
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+ * For some reason, the pixelvalve4 doesn't work with
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+ * the usual formula and will only work with 32.
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+ */
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+ if (vc4_crtc->data->hvs_output == 5)
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+ return 32;
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+
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return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
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}
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}
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@@ -281,8 +288,14 @@ static u32 vc4_crtc_get_fifo_full_level_
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u32 format)
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{
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u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
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- return VC4_SET_FIELD(level & 0x3f,
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- PV_CONTROL_FIFO_LEVEL);
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+ u32 ret = 0;
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+
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+ if (level > 0x3f)
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+ ret |= VC4_SET_FIELD((level >> 6) & 0x3,
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+ PV5_CONTROL_FIFO_LEVEL_HIGH);
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+
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+ return ret | VC4_SET_FIELD(level & 0x3f,
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+ PV_CONTROL_FIFO_LEVEL);
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}
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/*
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@@ -328,6 +341,9 @@ static void vc4_crtc_config_pv(struct dr
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CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
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CRTC_WRITE(PV_CONTROL, 0);
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+ CRTC_WRITE(PV_MUX_CFG,
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+ VC4_SET_FIELD(8, PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
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+
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CRTC_WRITE(PV_HORZA,
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VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
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PV_HORZA_HBP) |
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@@ -1115,10 +1131,72 @@ static const struct vc4_crtc_data bcm283
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},
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};
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+static const struct vc4_crtc_data bcm2711_pv0_data = {
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+ .debugfs_name = "crtc0_regs",
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+ .hvs_available_channels = BIT(0),
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+ .hvs_output = 0,
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+ .fifo_depth = 64,
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+ .pixels_per_clock = 1,
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+ .encoder_types = {
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+ [0] = VC4_ENCODER_TYPE_DSI0,
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+ [1] = VC4_ENCODER_TYPE_DPI,
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+ },
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+};
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+
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+static const struct vc4_crtc_data bcm2711_pv1_data = {
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+ .debugfs_name = "crtc1_regs",
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+ .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
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+ .hvs_output = 3,
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+ .fifo_depth = 64,
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+ .pixels_per_clock = 1,
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+ .encoder_types = {
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+ [0] = VC4_ENCODER_TYPE_DSI1,
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+ [1] = VC4_ENCODER_TYPE_SMI,
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+ },
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+};
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+
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+static const struct vc4_crtc_data bcm2711_pv2_data = {
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+ .debugfs_name = "crtc2_regs",
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+ .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
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+ .hvs_output = 4,
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+ .fifo_depth = 256,
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+ .pixels_per_clock = 2,
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+ .encoder_types = {
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+ [0] = VC4_ENCODER_TYPE_HDMI0,
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+ },
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+};
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+
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+static const struct vc4_crtc_data bcm2711_pv3_data = {
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+ .debugfs_name = "crtc3_regs",
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+ .hvs_available_channels = BIT(1),
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+ .hvs_output = 1,
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+ .fifo_depth = 64,
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+ .pixels_per_clock = 1,
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+ .encoder_types = {
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+ [0] = VC4_ENCODER_TYPE_VEC,
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+ },
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+};
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+
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+static const struct vc4_crtc_data bcm2711_pv4_data = {
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+ .debugfs_name = "crtc4_regs",
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+ .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
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+ .hvs_output = 5,
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+ .fifo_depth = 64,
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+ .pixels_per_clock = 2,
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+ .encoder_types = {
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+ [0] = VC4_ENCODER_TYPE_HDMI1,
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+ },
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+};
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+
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static const struct of_device_id vc4_crtc_dt_match[] = {
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{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
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{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
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{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
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+ { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
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+ { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
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+ { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
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+ { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
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+ { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
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{}
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};
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -130,6 +130,8 @@
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#define V3D_ERRSTAT 0x00f20
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#define PV_CONTROL 0x00
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+# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)
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+# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25
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# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
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# define PV_CONTROL_FORMAT_SHIFT 21
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# define PV_CONTROL_FORMAT_24 0
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@@ -209,6 +211,10 @@
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#define PV_HACT_ACT 0x30
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+#define PV_MUX_CFG 0x34
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+# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)
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+# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2
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+
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#define SCALER_CHANNELS_COUNT 3
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#define SCALER_DISPCTRL 0x00000000
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