mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 14:37:57 +00:00
5c69047aaf
Add clockdev lookup support for easier providing of clocks for devices. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
From cb86630379c8f3432c916d62045b5176f17f4123 Mon Sep 17 00:00:00 2001
|
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
|
Date: Sun, 16 Jul 2017 12:57:21 +0200
|
|
Subject: [PATCH V2 6/8] MIPS: BCM63XX: move the HSSPI PLL HZ into its own
|
|
clock
|
|
|
|
Split up the HSSPL clock into rate and a gate clock, to more closely
|
|
match the actual hardware.
|
|
|
|
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
|
---
|
|
arch/mips/bcm63xx/clk.c | 10 ++++++++--
|
|
1 file changed, 8 insertions(+), 2 deletions(-)
|
|
|
|
--- a/arch/mips/bcm63xx/clk.c
|
|
+++ b/arch/mips/bcm63xx/clk.c
|
|
@@ -247,6 +247,10 @@ static struct clk clk_hsspi = {
|
|
.set = hsspi_set,
|
|
};
|
|
|
|
+/*
|
|
+ * HSSPI PLL
|
|
+ */
|
|
+static struct clk clk_hsspi_pll;
|
|
|
|
/*
|
|
* XTM clock
|
|
@@ -373,6 +377,7 @@ static struct clk_lookup bcm6328_clks[]
|
|
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
|
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
|
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
|
|
+ CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
|
|
/* gated clocks */
|
|
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
|
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
|
@@ -440,6 +445,7 @@ static struct clk_lookup bcm6362_clks[]
|
|
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
|
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
|
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
|
|
+ CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
|
|
/* gated clocks */
|
|
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
|
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
|
@@ -474,7 +480,7 @@ static int __init bcm63xx_clk_init(void)
|
|
clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
|
|
break;
|
|
case BCM6328_CPU_ID:
|
|
- clk_hsspi.rate = HSSPI_PLL_HZ_6328;
|
|
+ clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
|
|
clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
|
|
break;
|
|
case BCM6338_CPU_ID:
|
|
@@ -490,7 +496,7 @@ static int __init bcm63xx_clk_init(void)
|
|
clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
|
|
break;
|
|
case BCM6362_CPU_ID:
|
|
- clk_hsspi.rate = HSSPI_PLL_HZ_6362;
|
|
+ clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
|
|
clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
|
|
break;
|
|
case BCM6368_CPU_ID:
|