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https://github.com/openwrt/openwrt.git
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37c2bc4397
* fix switch ports with modes other than 1000M/Full
* set 32-bit dma_coherent_mask to get PPE to work with 4 GiB of RAM
* sync driver for built-in 1GE PHY with MediaTek SDK sources
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 4ae2f43b3a
)
600 lines
20 KiB
Diff
600 lines
20 KiB
Diff
From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 2 Nov 2023 16:47:07 +0100
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Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields
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in mtk_soc_data struct
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Split tx and rx fields in mtk_soc_data struct. This is a preliminary
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patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang
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if the device receives a corrupted packet.
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +--
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2 files changed, 139 insertions(+), 100 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -1238,7 +1238,7 @@ static int mtk_init_fq_dma(struct mtk_et
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eth->scratch_ring = eth->sram_base;
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else
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eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
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- cnt * soc->txrx.txd_size,
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+ cnt * soc->tx.desc_size,
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ð->phy_scratch_ring,
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GFP_KERNEL);
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if (unlikely(!eth->scratch_ring))
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@@ -1254,16 +1254,16 @@ static int mtk_init_fq_dma(struct mtk_et
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if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
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return -ENOMEM;
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- phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
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+ phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
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for (i = 0; i < cnt; i++) {
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struct mtk_tx_dma_v2 *txd;
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- txd = eth->scratch_ring + i * soc->txrx.txd_size;
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+ txd = eth->scratch_ring + i * soc->tx.desc_size;
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txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
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if (i < cnt - 1)
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txd->txd2 = eth->phy_scratch_ring +
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- (i + 1) * soc->txrx.txd_size;
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+ (i + 1) * soc->tx.desc_size;
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txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
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txd->txd4 = 0;
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@@ -1510,7 +1510,7 @@ static int mtk_tx_map(struct sk_buff *sk
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if (itxd == ring->last_free)
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return -ENOMEM;
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- itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
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+ itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
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memset(itx_buf, 0, sizeof(*itx_buf));
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txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
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@@ -1551,7 +1551,7 @@ static int mtk_tx_map(struct sk_buff *sk
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memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
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txd_info.size = min_t(unsigned int, frag_size,
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- soc->txrx.dma_max_len);
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+ soc->tx.dma_max_len);
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txd_info.qid = queue;
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txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
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!(frag_size - txd_info.size);
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@@ -1564,7 +1564,7 @@ static int mtk_tx_map(struct sk_buff *sk
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mtk_tx_set_dma_desc(dev, txd, &txd_info);
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tx_buf = mtk_desc_to_tx_buf(ring, txd,
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- soc->txrx.txd_size);
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+ soc->tx.desc_size);
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if (new_desc)
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memset(tx_buf, 0, sizeof(*tx_buf));
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tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
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@@ -1607,7 +1607,7 @@ static int mtk_tx_map(struct sk_buff *sk
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} else {
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int next_idx;
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- next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
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+ next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
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ring->dma_size);
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mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
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}
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@@ -1616,7 +1616,7 @@ static int mtk_tx_map(struct sk_buff *sk
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err_dma:
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do {
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- tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
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+ tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
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/* unmap dma */
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mtk_tx_unmap(eth, tx_buf, false);
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@@ -1641,7 +1641,7 @@ static int mtk_cal_txd_req(struct mtk_et
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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frag = &skb_shinfo(skb)->frags[i];
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nfrags += DIV_ROUND_UP(skb_frag_size(frag),
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- eth->soc->txrx.dma_max_len);
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+ eth->soc->tx.dma_max_len);
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}
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} else {
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nfrags += skb_shinfo(skb)->nr_frags;
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@@ -1782,7 +1782,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
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ring = ð->rx_ring[i];
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idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
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- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
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+ rxd = ring->dma + idx * eth->soc->rx.desc_size;
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if (rxd->rxd2 & RX_DMA_DONE) {
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ring->calc_idx_update = true;
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return ring;
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@@ -1950,7 +1950,7 @@ static int mtk_xdp_submit_frame(struct m
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}
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htxd = txd;
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- tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
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+ tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
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memset(tx_buf, 0, sizeof(*tx_buf));
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htx_buf = tx_buf;
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@@ -1970,7 +1970,7 @@ static int mtk_xdp_submit_frame(struct m
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goto unmap;
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tx_buf = mtk_desc_to_tx_buf(ring, txd,
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- soc->txrx.txd_size);
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+ soc->tx.desc_size);
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memset(tx_buf, 0, sizeof(*tx_buf));
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n_desc++;
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}
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@@ -2007,7 +2007,7 @@ static int mtk_xdp_submit_frame(struct m
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} else {
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int idx;
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- idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
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+ idx = txd_to_idx(ring, txd, soc->tx.desc_size);
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mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
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MT7628_TX_CTX_IDX0);
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}
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@@ -2019,7 +2019,7 @@ static int mtk_xdp_submit_frame(struct m
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unmap:
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while (htxd != txd) {
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txd_pdma = qdma_to_pdma(ring, htxd);
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- tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
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+ tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
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mtk_tx_unmap(eth, tx_buf, false);
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htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
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@@ -2147,7 +2147,7 @@ static int mtk_poll_rx(struct napi_struc
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goto rx_done;
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idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
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- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
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+ rxd = ring->dma + idx * eth->soc->rx.desc_size;
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data = ring->data[idx];
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if (!mtk_rx_get_desc(eth, &trxd, rxd))
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@@ -2282,7 +2282,7 @@ static int mtk_poll_rx(struct napi_struc
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rxdcsum = &trxd.rxd4;
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}
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- if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
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+ if (*rxdcsum & eth->soc->rx.dma_l4_valid)
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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else
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skb_checksum_none_assert(skb);
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@@ -2403,7 +2403,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
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break;
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tx_buf = mtk_desc_to_tx_buf(ring, desc,
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- eth->soc->txrx.txd_size);
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+ eth->soc->tx.desc_size);
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if (!tx_buf->data)
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break;
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@@ -2451,7 +2451,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
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}
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mtk_tx_unmap(eth, tx_buf, true);
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- desc = ring->dma + cpu * eth->soc->txrx.txd_size;
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+ desc = ring->dma + cpu * eth->soc->tx.desc_size;
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ring->last_free = desc;
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atomic_inc(&ring->free_count);
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@@ -2540,7 +2540,7 @@ static int mtk_napi_rx(struct napi_struc
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do {
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int rx_done;
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- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
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+ mtk_w32(eth, eth->soc->rx.irq_done_mask,
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reg_map->pdma.irq_status);
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rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
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rx_done_total += rx_done;
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@@ -2556,10 +2556,10 @@ static int mtk_napi_rx(struct napi_struc
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return budget;
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} while (mtk_r32(eth, reg_map->pdma.irq_status) &
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- eth->soc->txrx.rx_irq_done_mask);
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+ eth->soc->rx.irq_done_mask);
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if (napi_complete_done(napi, rx_done_total))
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- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
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+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
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return rx_done_total;
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}
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@@ -2568,7 +2568,7 @@ static int mtk_tx_alloc(struct mtk_eth *
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{
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const struct mtk_soc_data *soc = eth->soc;
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struct mtk_tx_ring *ring = ð->tx_ring;
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- int i, sz = soc->txrx.txd_size;
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+ int i, sz = soc->tx.desc_size;
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struct mtk_tx_dma_v2 *txd;
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int ring_size;
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u32 ofs, val;
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@@ -2691,14 +2691,14 @@ static void mtk_tx_clean(struct mtk_eth
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}
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if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
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dma_free_coherent(eth->dma_dev,
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- ring->dma_size * soc->txrx.txd_size,
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+ ring->dma_size * soc->tx.desc_size,
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ring->dma, ring->phys);
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ring->dma = NULL;
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}
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if (ring->dma_pdma) {
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dma_free_coherent(eth->dma_dev,
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- ring->dma_size * soc->txrx.txd_size,
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+ ring->dma_size * soc->tx.desc_size,
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ring->dma_pdma, ring->phys_pdma);
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ring->dma_pdma = NULL;
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}
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@@ -2753,15 +2753,15 @@ static int mtk_rx_alloc(struct mtk_eth *
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if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
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rx_flag != MTK_RX_FLAGS_NORMAL) {
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ring->dma = dma_alloc_coherent(eth->dma_dev,
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- rx_dma_size * eth->soc->txrx.rxd_size,
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- &ring->phys, GFP_KERNEL);
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+ rx_dma_size * eth->soc->rx.desc_size,
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+ &ring->phys, GFP_KERNEL);
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} else {
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struct mtk_tx_ring *tx_ring = ð->tx_ring;
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ring->dma = tx_ring->dma + tx_ring_size *
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- eth->soc->txrx.txd_size * (ring_no + 1);
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+ eth->soc->tx.desc_size * (ring_no + 1);
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ring->phys = tx_ring->phys + tx_ring_size *
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- eth->soc->txrx.txd_size * (ring_no + 1);
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+ eth->soc->tx.desc_size * (ring_no + 1);
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}
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if (!ring->dma)
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@@ -2772,7 +2772,7 @@ static int mtk_rx_alloc(struct mtk_eth *
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dma_addr_t dma_addr;
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void *data;
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- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
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+ rxd = ring->dma + i * eth->soc->rx.desc_size;
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if (ring->page_pool) {
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data = mtk_page_pool_get_buff(ring->page_pool,
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&dma_addr, GFP_KERNEL);
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@@ -2861,7 +2861,7 @@ static void mtk_rx_clean(struct mtk_eth
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if (!ring->data[i])
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continue;
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- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
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+ rxd = ring->dma + i * eth->soc->rx.desc_size;
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if (!rxd->rxd1)
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continue;
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@@ -2878,7 +2878,7 @@ static void mtk_rx_clean(struct mtk_eth
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if (!in_sram && ring->dma) {
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dma_free_coherent(eth->dma_dev,
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- ring->dma_size * eth->soc->txrx.rxd_size,
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+ ring->dma_size * eth->soc->rx.desc_size,
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ring->dma, ring->phys);
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ring->dma = NULL;
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}
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@@ -3241,7 +3241,7 @@ static void mtk_dma_free(struct mtk_eth
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netdev_reset_queue(eth->netdev[i]);
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if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
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dma_free_coherent(eth->dma_dev,
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- MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
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+ MTK_QDMA_RING_SIZE * soc->tx.desc_size,
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eth->scratch_ring, eth->phy_scratch_ring);
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eth->scratch_ring = NULL;
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eth->phy_scratch_ring = 0;
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@@ -3291,7 +3291,7 @@ static irqreturn_t mtk_handle_irq_rx(int
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eth->rx_events++;
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if (likely(napi_schedule_prep(ð->rx_napi))) {
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- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
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+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
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__napi_schedule(ð->rx_napi);
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}
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@@ -3317,9 +3317,9 @@ static irqreturn_t mtk_handle_irq(int ir
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const struct mtk_reg_map *reg_map = eth->soc->reg_map;
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if (mtk_r32(eth, reg_map->pdma.irq_mask) &
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- eth->soc->txrx.rx_irq_done_mask) {
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+ eth->soc->rx.irq_done_mask) {
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if (mtk_r32(eth, reg_map->pdma.irq_status) &
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- eth->soc->txrx.rx_irq_done_mask)
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+ eth->soc->rx.irq_done_mask)
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mtk_handle_irq_rx(irq, _eth);
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}
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if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
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@@ -3337,10 +3337,10 @@ static void mtk_poll_controller(struct n
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struct mtk_eth *eth = mac->hw;
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mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
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- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
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+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
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mtk_handle_irq_rx(eth->irq[2], dev);
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mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
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- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
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+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
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}
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#endif
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@@ -3505,7 +3505,7 @@ static int mtk_open(struct net_device *d
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napi_enable(ð->tx_napi);
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napi_enable(ð->rx_napi);
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mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
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- mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
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+ mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
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refcount_set(ð->dma_refcnt, 1);
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}
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else
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@@ -3588,7 +3588,7 @@ static int mtk_stop(struct net_device *d
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mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
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mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
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- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
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+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
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napi_disable(ð->tx_napi);
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napi_disable(ð->rx_napi);
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@@ -4064,9 +4064,9 @@ static int mtk_hw_init(struct mtk_eth *e
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/* FE int grouping */
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mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
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- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
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+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
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mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
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- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
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+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
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mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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if (mtk_is_netsys_v3_or_greater(eth)) {
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@@ -5166,11 +5166,15 @@ static const struct mtk_soc_data mt2701_
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.required_clks = MT7623_CLKS_BITMAP,
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.required_pctl = true,
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.version = 1,
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- .txrx = {
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- .txd_size = sizeof(struct mtk_tx_dma),
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- .rxd_size = sizeof(struct mtk_rx_dma),
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- .rx_irq_done_mask = MTK_RX_DONE_INT,
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- .rx_dma_l4_valid = RX_DMA_L4_VALID,
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+ .tx = {
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+ .desc_size = sizeof(struct mtk_tx_dma),
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+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
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+ .dma_len_offset = 16,
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+ },
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+ .rx = {
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+ .desc_size = sizeof(struct mtk_rx_dma),
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+ .irq_done_mask = MTK_RX_DONE_INT,
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+ .dma_l4_valid = RX_DMA_L4_VALID,
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.dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
.dma_len_offset = 16,
|
|
},
|
|
@@ -5186,11 +5190,15 @@ static const struct mtk_soc_data mt7621_
|
|
.offload_version = 1,
|
|
.hash_offset = 2,
|
|
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
+ .dma_len_offset = 16,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
.dma_len_offset = 16,
|
|
},
|
|
@@ -5208,11 +5216,15 @@ static const struct mtk_soc_data mt7622_
|
|
.hash_offset = 2,
|
|
.has_accounting = true,
|
|
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
+ .dma_len_offset = 16,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
.dma_len_offset = 16,
|
|
},
|
|
@@ -5229,11 +5241,15 @@ static const struct mtk_soc_data mt7623_
|
|
.hash_offset = 2,
|
|
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
|
|
.disable_pll_modes = true,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
+ .dma_len_offset = 16,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
.dma_len_offset = 16,
|
|
},
|
|
@@ -5248,11 +5264,15 @@ static const struct mtk_soc_data mt7629_
|
|
.required_pctl = false,
|
|
.has_accounting = true,
|
|
.version = 1,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
+ .dma_len_offset = 16,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
.dma_len_offset = 16,
|
|
},
|
|
@@ -5270,11 +5290,15 @@ static const struct mtk_soc_data mt7981_
|
|
.hash_offset = 4,
|
|
.has_accounting = true,
|
|
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma_v2),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma_v2),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma_v2),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
|
|
+ .dma_len_offset = 8,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma_v2),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT_V2,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
|
|
.dma_len_offset = 8,
|
|
},
|
|
@@ -5292,11 +5316,15 @@ static const struct mtk_soc_data mt7986_
|
|
.hash_offset = 4,
|
|
.has_accounting = true,
|
|
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma_v2),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma_v2),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma_v2),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
|
|
+ .dma_len_offset = 8,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma_v2),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT_V2,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
|
|
.dma_len_offset = 8,
|
|
},
|
|
@@ -5314,11 +5342,15 @@ static const struct mtk_soc_data mt7988_
|
|
.hash_offset = 4,
|
|
.has_accounting = true,
|
|
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma_v2),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma_v2),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma_v2),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
|
|
+ .dma_len_offset = 8,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma_v2),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT_V2,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
|
|
.dma_len_offset = 8,
|
|
},
|
|
@@ -5331,11 +5363,15 @@ static const struct mtk_soc_data rt5350_
|
|
.required_clks = MT7628_CLKS_BITMAP,
|
|
.required_pctl = false,
|
|
.version = 1,
|
|
- .txrx = {
|
|
- .txd_size = sizeof(struct mtk_tx_dma),
|
|
- .rxd_size = sizeof(struct mtk_rx_dma),
|
|
- .rx_irq_done_mask = MTK_RX_DONE_INT,
|
|
- .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
|
|
+ .tx = {
|
|
+ .desc_size = sizeof(struct mtk_tx_dma),
|
|
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
+ .dma_len_offset = 16,
|
|
+ },
|
|
+ .rx = {
|
|
+ .desc_size = sizeof(struct mtk_rx_dma),
|
|
+ .irq_done_mask = MTK_RX_DONE_INT,
|
|
+ .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
|
|
.dma_max_len = MTK_TX_DMA_BUF_LEN,
|
|
.dma_len_offset = 16,
|
|
},
|
|
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
@@ -326,8 +326,8 @@
|
|
/* QDMA descriptor txd3 */
|
|
#define TX_DMA_OWNER_CPU BIT(31)
|
|
#define TX_DMA_LS0 BIT(30)
|
|
-#define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
|
|
-#define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len)
|
|
+#define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
|
|
+#define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len)
|
|
#define TX_DMA_SWC BIT(14)
|
|
#define TX_DMA_PQID GENMASK(3, 0)
|
|
#define TX_DMA_ADDR64_MASK GENMASK(3, 0)
|
|
@@ -347,8 +347,8 @@
|
|
/* QDMA descriptor rxd2 */
|
|
#define RX_DMA_DONE BIT(31)
|
|
#define RX_DMA_LSO BIT(30)
|
|
-#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
|
|
-#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
|
|
+#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
|
|
+#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
|
|
#define RX_DMA_VTAG BIT(15)
|
|
#define RX_DMA_ADDR64_MASK GENMASK(3, 0)
|
|
#if IS_ENABLED(CONFIG_64BIT)
|
|
@@ -1279,10 +1279,9 @@ struct mtk_reg_map {
|
|
* @foe_entry_size Foe table entry size.
|
|
* @has_accounting Bool indicating support for accounting of
|
|
* offloaded flows.
|
|
- * @txd_size Tx DMA descriptor size.
|
|
- * @rxd_size Rx DMA descriptor size.
|
|
- * @rx_irq_done_mask Rx irq done register mask.
|
|
- * @rx_dma_l4_valid Rx DMA valid register mask.
|
|
+ * @desc_size Tx/Rx DMA descriptor size.
|
|
+ * @irq_done_mask Rx irq done register mask.
|
|
+ * @dma_l4_valid Rx DMA valid register mask.
|
|
* @dma_max_len Max DMA tx/rx buffer length.
|
|
* @dma_len_offset Tx/Rx DMA length field offset.
|
|
*/
|
|
@@ -1300,13 +1299,17 @@ struct mtk_soc_data {
|
|
bool has_accounting;
|
|
bool disable_pll_modes;
|
|
struct {
|
|
- u32 txd_size;
|
|
- u32 rxd_size;
|
|
- u32 rx_irq_done_mask;
|
|
- u32 rx_dma_l4_valid;
|
|
+ u32 desc_size;
|
|
u32 dma_max_len;
|
|
u32 dma_len_offset;
|
|
- } txrx;
|
|
+ } tx;
|
|
+ struct {
|
|
+ u32 desc_size;
|
|
+ u32 irq_done_mask;
|
|
+ u32 dma_l4_valid;
|
|
+ u32 dma_max_len;
|
|
+ u32 dma_len_offset;
|
|
+ } rx;
|
|
};
|
|
|
|
#define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
|