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6bcd1c2501
Some local patches have been sent to upstream and they are slightly different from the upstream version. So it's better to replace them to avoid conflicts with the new mac80211 backport driver. The different parts have been merged into patch 996. This commit also includes some additional fixes: * Fix watchdog function. * Improve MT7620 register initialization. * Introduce DMA busy watchdog for rt2800. P.S. Sometimes rt2800 series chips may fall into a DMA busy state. The tx queues become very slow and the client cannot connect to the AP. Usually, We can see a lot of hostapd warnings at this point: 'hostapd: IEEE 802.11: did not acknowledge authentication response' The DMA busy watchdog can help the driver automatically recover from this abnormal state. By the way, setting higer 'cell_density' and disabling 'disassoc_low_ack' can significantly reduce the probability of the DMA busy. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
147 lines
5.2 KiB
Diff
147 lines
5.2 KiB
Diff
From a28533c6be1711584bf3ec978309d5c590029821 Mon Sep 17 00:00:00 2001
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From: Shiji Yang <yangshiji66@outlook.com>
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Date: Thu, 19 Oct 2023 19:58:57 +0800
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Subject: wifi: rt2x00: rework MT7620 channel config function
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1. Move the channel configuration code from rt2800_vco_calibration()
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to the rt2800_config_channel().
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2. Use MT7620 SoC specific AGC initial LNA value instead of the
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RT5592's value.
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3. BBP{195,196} pairing write has been replaced with
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rt2800_bbp_glrt_write() to reduce redundant code.
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/TYAP286MB0315622A4340BFFA530B1B86BCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
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---
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drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 91 ++++++++++----------------
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1 file changed, 35 insertions(+), 56 deletions(-)
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--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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@@ -3861,14 +3861,6 @@ static void rt2800_config_channel_rf7620
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rfcsr |= tx_agc_fc;
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rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
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}
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-
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- if (conf_is_ht40(conf)) {
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- rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
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- rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
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- } else {
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- rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
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- rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
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- }
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}
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static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
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@@ -4437,32 +4429,46 @@ static void rt2800_config_channel(struct
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usleep_range(1000, 1500);
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}
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- if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
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- reg = 0x10;
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- if (!conf_is_ht40(conf)) {
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- if (rt2x00_rt(rt2x00dev, RT6352) &&
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- rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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- reg |= 0x5;
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- } else {
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- reg |= 0xa;
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- }
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- }
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- rt2800_bbp_write(rt2x00dev, 195, 141);
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- rt2800_bbp_write(rt2x00dev, 196, reg);
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+ if (rt2x00_rt(rt2x00dev, RT5592)) {
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+ bbp = conf_is_ht40(conf) ? 0x10 : 0x1a;
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+ rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
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- /* AGC init.
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- * Despite the vendor driver using different values here for
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- * RT6352 chip, we use 0x1c for now. This may have to be changed
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- * once TSSI got implemented.
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- */
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- reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
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- rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
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+ bbp = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
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+ rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
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- if (rt2x00_rt(rt2x00dev, RT5592))
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- rt2800_iq_calibrate(rt2x00dev, rf->channel);
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+ rt2800_iq_calibrate(rt2x00dev, rf->channel);
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}
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if (rt2x00_rt(rt2x00dev, RT6352)) {
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+ /* BBP for GLRT BW */
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+ bbp = conf_is_ht40(conf) ?
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+ 0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
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+ 0x15 : 0x1a;
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+ rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
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+
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+ bbp = conf_is_ht40(conf) ? 0x2f : 0x40;
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+ rt2800_bbp_glrt_write(rt2x00dev, 157, bbp);
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+
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+ if (rt2x00dev->default_ant.rx_chain_num == 1) {
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+ rt2800_bbp_write(rt2x00dev, 91, 0x07);
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+ rt2800_bbp_write(rt2x00dev, 95, 0x1a);
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+ rt2800_bbp_glrt_write(rt2x00dev, 128, 0xa0);
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+ rt2800_bbp_glrt_write(rt2x00dev, 170, 0x12);
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+ rt2800_bbp_glrt_write(rt2x00dev, 171, 0x10);
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+ } else {
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+ rt2800_bbp_write(rt2x00dev, 91, 0x06);
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+ rt2800_bbp_write(rt2x00dev, 95, 0x9a);
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+ rt2800_bbp_glrt_write(rt2x00dev, 128, 0xe0);
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+ rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
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+ rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
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+ }
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+
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+ /* AGC init */
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+ bbp = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
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+ rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
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+
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+ usleep_range(1000, 1500);
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+
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if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
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&rt2x00dev->cap_flags)) {
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reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
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@@ -5608,26 +5614,6 @@ void rt2800_vco_calibration(struct rt2x0
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rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
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if (rt2x00_rt(rt2x00dev, RT6352)) {
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- if (rt2x00dev->default_ant.rx_chain_num == 1) {
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- rt2800_bbp_write(rt2x00dev, 91, 0x07);
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- rt2800_bbp_write(rt2x00dev, 95, 0x1A);
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- rt2800_bbp_write(rt2x00dev, 195, 128);
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- rt2800_bbp_write(rt2x00dev, 196, 0xA0);
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- rt2800_bbp_write(rt2x00dev, 195, 170);
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- rt2800_bbp_write(rt2x00dev, 196, 0x12);
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- rt2800_bbp_write(rt2x00dev, 195, 171);
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- rt2800_bbp_write(rt2x00dev, 196, 0x10);
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- } else {
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- rt2800_bbp_write(rt2x00dev, 91, 0x06);
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- rt2800_bbp_write(rt2x00dev, 95, 0x9A);
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- rt2800_bbp_write(rt2x00dev, 195, 128);
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- rt2800_bbp_write(rt2x00dev, 196, 0xE0);
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- rt2800_bbp_write(rt2x00dev, 195, 170);
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- rt2800_bbp_write(rt2x00dev, 196, 0x30);
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- rt2800_bbp_write(rt2x00dev, 195, 171);
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- rt2800_bbp_write(rt2x00dev, 196, 0x30);
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- }
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-
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if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_bbp_write(rt2x00dev, 75, 0x68);
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rt2800_bbp_write(rt2x00dev, 76, 0x4C);
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@@ -5635,13 +5621,6 @@ void rt2800_vco_calibration(struct rt2x0
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rt2800_bbp_write(rt2x00dev, 80, 0x0C);
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rt2800_bbp_write(rt2x00dev, 82, 0xB6);
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}
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-
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- /* On 11A, We should delay and wait RF/BBP to be stable
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- * and the appropriate time should be 1000 micro seconds
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- * 2005/06/05 - On 11G, we also need this delay time.
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- * Otherwise it's difficult to pass the WHQL.
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- */
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- usleep_range(1000, 1500);
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}
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}
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EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
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