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c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DT_BINDINGS_SF21_IOMUX_H__
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#define __DT_BINDINGS_SF21_IOMUX_H__
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#define SW_DS 0xf /* Drive strength */
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#define SW_ST (1 << 4) /* Schmitt enable */
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#define SW_PD (1 << 5) /* Pull-down enable */
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#define SW_PU (1 << 6) /* Pull-up enable */
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#define SW_OEN (1 << 7) /* Output disable [sic] */
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#define SW_IE (1 << 8) /* Input enable */
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#define MODE_BIT0 (1 << 9) /* Function mode LSB */
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#define MODE_BIT1 (1 << 10) /* Function mode MSB */
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#define FMUX_SEL (1 << 11) /* GPIO mode enable */
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#define FUNC_SW_SEL (1 << 12) /* Function mode enable */
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#define FUNC_MODE_MASK 0x1f80
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#define FUNC_MODE0 (FUNC_SW_SEL | SW_IE)
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#define FUNC_MODE1 (FUNC_MODE0 | MODE_BIT0)
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#define FUNC_MODE2 (FUNC_MODE0 | MODE_BIT1)
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#define FUNC_MODE3 (FUNC_MODE0 | MODE_BIT0 | MODE_BIT1)
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#define GPIO_MODE (FUNC_MODE0 | FMUX_SEL)
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#define EXT_CLK_IN 0x00
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#define CLK_OUT 0x04
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#define SPI0_TXD 0x08
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#define SPI0_RXD 0x0c
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#define SPI0_CLK 0x10
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#define SPI0_CSN 0x14
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#define SPI0_HOLD 0x18
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#define SPI0_WP 0x1c
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#define JTAG_TDO 0x20
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#define JTAG_TDI 0x24
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#define JTAG_TMS 0x28
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#define JTAG_TCK 0x2c
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#define JTAG_RST 0x30
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#define UART1_TX 0x34
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#define UART1_RX 0x38
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#define I2C0_DAT 0x3c
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#define I2C0_CLK 0x40
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#define I2C1_DAT 0x44
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#define I2C1_CLK 0x48
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#define PWM0 0x4c
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#define PWM1 0x50
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#define RGMII_GTX_CLK 0x54
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#define RGMII_TXCLK 0x58
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#define RGMII_TXD0 0x5c
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#define RGMII_TXD1 0x60
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#define RGMII_TXD2 0x64
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#define RGMII_TXD3 0x68
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#define RGMII_TXCTL 0x6c
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#define RGMII_RXCLK 0x70
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#define RGMII_RXD0 0x74
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#define RGMII_RXD1 0x78
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#define RGMII_RXD2 0x7c
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#define RGMII_RXD3 0x80
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#define RGMII_RXCTL 0x84
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#define QSGMII_MDIO 0x88
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#define QSGMII_MDC 0x8c
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#define SXGMII_MDIO 0x90
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#define SXGMII_MDC 0x94
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#define DGS_INT 0x98
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#define PHY_RSTN 0x9c
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#define PHY_INT 0xa0
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#endif
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