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c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
143 lines
3.2 KiB
C
143 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/mfd/syscon.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <dt-bindings/reset/siflower,sf21-reset.h>
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#define SF21_SOFT_RESET 0xC0
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struct sf21_reset_data {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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static inline int sf21_reset_shift(unsigned long id)
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{
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switch (id) {
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case SF21_RESET_GIC:
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case SF21_RESET_AXI:
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case SF21_RESET_AHB:
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case SF21_RESET_APB:
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case SF21_RESET_IRAM:
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return id + 1;
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case SF21_RESET_NPU:
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case SF21_RESET_DDR_CTL:
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case SF21_RESET_DDR_PHY:
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case SF21_RESET_DDR_PWR_OK_IN:
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case SF21_RESET_DDR_CTL_APB:
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case SF21_RESET_DDR_PHY_APB:
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return id + 2;
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case SF21_RESET_USB:
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return id + 8;
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case SF21_RESET_PVT:
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case SF21_RESET_SERDES_CSR:
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return id + 11;
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case SF21_RESET_CRYPT_CSR:
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case SF21_RESET_CRYPT_APP:
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case SF21_RESET_NPU2DDR_ASYNCBRIDGE:
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case SF21_RESET_IROM:
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return id + 14;
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default:
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return -EINVAL;
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}
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}
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static int sf21_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct sf21_reset_data *rd;
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int shift;
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u32 mask;
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rd = container_of(rcdev, struct sf21_reset_data, rcdev);
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shift = sf21_reset_shift(id);
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mask = BIT(shift);
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return regmap_update_bits(rd->regmap, SF21_SOFT_RESET, mask, 0);
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}
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static int sf21_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct sf21_reset_data *rd;
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int shift;
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u32 mask;
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rd = container_of(rcdev, struct sf21_reset_data, rcdev);
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shift = sf21_reset_shift(id);
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mask = BIT(shift);
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return regmap_update_bits(rd->regmap, SF21_SOFT_RESET, mask, mask);
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}
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static int sf21_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct sf21_reset_data *rd;
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int shift, ret;
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u32 mask;
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u32 reg;
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rd = container_of(rcdev, struct sf21_reset_data, rcdev);
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ret = regmap_read(rd->regmap, SF21_SOFT_RESET, ®);
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if (ret)
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return ret;
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shift = sf21_reset_shift(id);
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mask = BIT(shift);
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return !!(reg & mask);
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}
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static const struct reset_control_ops sf21_reset_ops = {
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.assert = sf21_reset_assert,
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.deassert = sf21_reset_deassert,
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.status = sf21_reset_status,
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};
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static int sf21_reset_probe(struct platform_device *pdev)
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{
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struct sf21_reset_data *rd;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct device_node *node;
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rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL);
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if (!rd)
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return -ENOMEM;
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node = of_parse_phandle(np, "siflower,crm", 0);
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rd->regmap = syscon_node_to_regmap(node);
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if (IS_ERR(rd->regmap))
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return PTR_ERR(rd->regmap);
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rd->rcdev.owner = THIS_MODULE;
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rd->rcdev.nr_resets = SF21_RESET_MAX + 1;
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rd->rcdev.ops = &sf21_reset_ops;
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rd->rcdev.of_node = np;
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return devm_reset_controller_register(dev, &rd->rcdev);
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}
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static const struct of_device_id sf21_reset_dt_ids[] = {
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{ .compatible = "siflower,sf21-reset" },
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{},
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};
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static struct platform_driver sf21_reset_driver = {
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.probe = sf21_reset_probe,
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.driver = {
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.name = "sf21-reset",
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.of_match_table = sf21_reset_dt_ids,
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},
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};
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builtin_platform_driver(sf21_reset_driver);
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