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This board is also as known as SuperElectron ZN-M5 and ZN-M8. However, for ZN-M5 and ZN-M8, there's another version uses ZX279128 as CPU chip, which is unsupported. You can check it in "高级设置" > "系统日志" > "内核日志" page from webUI. Hardware specification: SoC: MediaTek MT7981B 2x A53 Flash: 128 MB SPI-NAND RAM: 256MB Ethernet: 4x 10/100/1000 Mbps Switch: MediaTek MT7531AE WiFi: MediaTek MT7976C Button: Reset, WPS Power: DC 12V 1A Stock layout flash instructions: Login into webUI and upload sysupgrade firmware in "系统管理" > "升级固件" page. Remember to unselect "保留配置" ("Keep configurations") first before doing that. OpenWrt U-Boot layout flash instructions: 1. Flash stock layout firmware first. 2. Connect to the device via SSH, and backup everything, especially 'Factory' partition. 3. Unlock MTD partitions: apk update && apk add kmod-mtd-rw insmod mtd-rw i_want_a_brick=1 4. Write new BL2 and FIP: mtd write openwrt-mediatek-filogic-cmcc_a10-ubootmod-preloader.bin BL2 mtd write openwrt-mediatek-filogic-cmcc_a10-ubootmod-bl31-uboot.fip FIP 5. Set static IP on your PC: IP 192.168.1.254/24, GW 192.168.1.1 6. Serve OpenWrt initramfs image using TFTP server. 7. Cut off the power and re-engage, wait for TFTP recovery to complete. 8. After OpenWrt has booted, perform sysupgrade. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/18121 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
255 lines
4.2 KiB
Plaintext
255 lines
4.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (C) 2023 Tianling Shen <cnsztl@immortalwrt.org>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "mt7981.dtsi"
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/ {
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aliases {
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led-boot = &boot_led;
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led-failsafe = &boot_led;
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led-running = &running_led;
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led-upgrade = &running_led;
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serial0 = &uart0;
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};
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chosen: chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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reg = <0 0x40000000 0 0x10000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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button-reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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};
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button-wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_BLUE>;
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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running_led: led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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boot_led: led-2 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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gpios = <&pio 11 GPIO_ACTIVE_LOW>;
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};
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};
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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nvmem-cells = <&macaddr_factory_2a 0>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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&mdio_bus {
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switch: switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&pio {
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spi0_flash_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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status = "okay";
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spi_nand: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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partitions: partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "BL2";
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reg = <0x0 0x100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x100000 0x80000>;
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};
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partition@180000 {
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label = "Factory";
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reg = <0x180000 0x200000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x1000>;
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};
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macaddr_factory_a: macaddr@a {
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compatible = "mac-base";
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reg = <0xa 0x6>;
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#nvmem-cell-cells = <1>;
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};
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macaddr_factory_24: macaddr@24 {
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compatible = "mac-base";
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reg = <0x24 0x6>;
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#nvmem-cell-cells = <1>;
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};
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macaddr_factory_2a: macaddr@2a {
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compatible = "mac-base";
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reg = <0x2a 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@380000 {
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label = "FIP";
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reg = <0x380000 0x200000>;
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read-only;
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};
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};
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};
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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nvmem-cells = <&macaddr_factory_24 0>;
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nvmem-cell-names = "mac-address";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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status = "okay";
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band@1 {
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reg = <1>;
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nvmem-cells = <&macaddr_factory_a 0>;
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nvmem-cell-names = "mac-address";
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};
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};
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