mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
3711557bdf
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.36
Manually rebased:
generic/hack-6.6/765-mxl-gpy-control-LED-reg-from-DT.patch
bcm27xx/patches-6.6/950-0536-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch
Removed upstreamed:
bmips/patches-6.6/010-v6.10-mips-bmips-BCM6358-make-sure-CBR-is-correctly-set.patch[1]
All other patches automatically rebased.
1. 7c9644a7b5
Build system: x86/64
Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Signed-off-by: John Audia <therealgraysky@proton.me>
152 lines
4.6 KiB
Diff
152 lines
4.6 KiB
Diff
From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
|
|
From: Balsam CHIHI <bchihi@baylibre.com>
|
|
Date: Tue, 17 Oct 2023 21:05:43 +0200
|
|
Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
|
|
support
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Add LVTS Driver support for MT8192.
|
|
|
|
Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
|
|
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
|
|
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
|
|
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
|
|
[bero@baylibre.com: cosmetic changes, rebase]
|
|
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
|
|
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
|
|
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
|
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
|
Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
|
|
---
|
|
drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
|
|
1 file changed, 95 insertions(+)
|
|
|
|
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
|
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
|
@@ -92,6 +92,7 @@
|
|
#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
|
|
|
|
#define LVTS_HW_SHUTDOWN_MT7988 105000
|
|
+#define LVTS_HW_SHUTDOWN_MT8192 105000
|
|
#define LVTS_HW_SHUTDOWN_MT8195 105000
|
|
|
|
#define LVTS_MINIMUM_THRESHOLD 20000
|
|
@@ -1335,6 +1336,88 @@ static int lvts_resume(struct device *de
|
|
return 0;
|
|
}
|
|
|
|
+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
|
|
+ {
|
|
+ .cal_offset = { 0x04, 0x08 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT8192_MCU_BIG_CPU0 },
|
|
+ { .dt_id = MT8192_MCU_BIG_CPU1 }
|
|
+ },
|
|
+ .num_lvts_sensor = 2,
|
|
+ .offset = 0x0,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
|
+ .mode = LVTS_MSR_FILTERED_MODE,
|
|
+ },
|
|
+ {
|
|
+ .cal_offset = { 0x0c, 0x10 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT8192_MCU_BIG_CPU2 },
|
|
+ { .dt_id = MT8192_MCU_BIG_CPU3 }
|
|
+ },
|
|
+ .num_lvts_sensor = 2,
|
|
+ .offset = 0x100,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
|
+ .mode = LVTS_MSR_FILTERED_MODE,
|
|
+ },
|
|
+ {
|
|
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
|
|
+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
|
|
+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
|
|
+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
|
|
+ },
|
|
+ .num_lvts_sensor = 4,
|
|
+ .offset = 0x200,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
|
+ .mode = LVTS_MSR_FILTERED_MODE,
|
|
+ }
|
|
+};
|
|
+
|
|
+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
|
|
+ {
|
|
+ .cal_offset = { 0x24, 0x28 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT8192_AP_VPU0 },
|
|
+ { .dt_id = MT8192_AP_VPU1 }
|
|
+ },
|
|
+ .num_lvts_sensor = 2,
|
|
+ .offset = 0x0,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
|
+ },
|
|
+ {
|
|
+ .cal_offset = { 0x2c, 0x30 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT8192_AP_GPU0 },
|
|
+ { .dt_id = MT8192_AP_GPU1 }
|
|
+ },
|
|
+ .num_lvts_sensor = 2,
|
|
+ .offset = 0x100,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
|
+ },
|
|
+ {
|
|
+ .cal_offset = { 0x34, 0x38 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT8192_AP_INFRA },
|
|
+ { .dt_id = MT8192_AP_CAM },
|
|
+ },
|
|
+ .num_lvts_sensor = 2,
|
|
+ .offset = 0x200,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
|
+ },
|
|
+ {
|
|
+ .cal_offset = { 0x3c, 0x40, 0x44 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT8192_AP_MD0 },
|
|
+ { .dt_id = MT8192_AP_MD1 },
|
|
+ { .dt_id = MT8192_AP_MD2 }
|
|
+ },
|
|
+ .num_lvts_sensor = 3,
|
|
+ .offset = 0x300,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
|
+ }
|
|
+};
|
|
+
|
|
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
|
|
{
|
|
.cal_offset = { 0x04, 0x07 },
|
|
@@ -1421,6 +1504,16 @@ static const struct lvts_data mt7988_lvt
|
|
.temp_offset = LVTS_COEFF_B_MT7988,
|
|
};
|
|
|
|
+static const struct lvts_data mt8192_lvts_mcu_data = {
|
|
+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
|
|
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
|
|
+};
|
|
+
|
|
+static const struct lvts_data mt8192_lvts_ap_data = {
|
|
+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
|
|
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
|
|
+};
|
|
+
|
|
static const struct lvts_data mt8195_lvts_mcu_data = {
|
|
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
|
|
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
|
|
@@ -1437,6 +1530,8 @@ static const struct lvts_data mt8195_lvt
|
|
|
|
static const struct of_device_id lvts_of_match[] = {
|
|
{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
|
|
+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
|
|
+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
|
|
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
|
|
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
|
|
{},
|