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332 lines
8.5 KiB
Diff
332 lines
8.5 KiB
Diff
From 707ab07695ea8953a5bb56512e7bb38ca79c5c38 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Thu, 19 Feb 2015 23:27:59 +0100
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Subject: [PATCH V2] ARM: BCM5301X: Implement SMP support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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V2: Change code after receiving Florian's comments:
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1) Use "mmio-sram"
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2) Remove commented out ASM call
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3) Fix coding style in ASM
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4) Simplify finding OF node
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---
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Documentation/devicetree/bindings/arm/bcm4708.txt | 24 ++++
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Documentation/devicetree/bindings/arm/cpus.txt | 1 +
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arch/arm/boot/dts/bcm4708.dtsi | 13 ++
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arch/arm/mach-bcm/Makefile | 3 +
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arch/arm/mach-bcm/bcm5301x_headsmp.S | 45 ++++++
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arch/arm/mach-bcm/bcm5301x_smp.c | 158 ++++++++++++++++++++++
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6 files changed, 244 insertions(+)
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create mode 100644 arch/arm/mach-bcm/bcm5301x_headsmp.S
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create mode 100644 arch/arm/mach-bcm/bcm5301x_smp.c
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diff --git a/Documentation/devicetree/bindings/arm/bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm4708.txt
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index 6b0f49f..3dd0e9d 100644
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--- a/Documentation/devicetree/bindings/arm/bcm4708.txt
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+++ b/Documentation/devicetree/bindings/arm/bcm4708.txt
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@@ -6,3 +6,27 @@ Boards with the BCM4708 SoC shall have the following properties:
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Required root node property:
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compatible = "brcm,bcm4708";
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+
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+Optional sub-node properties:
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+
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+compatible = "mmio-sram" for SRAM access with IO memory region
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+ This is needed for SMP-capable SoCs which use part of
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+ SRAM for storing location of code to be executed by the
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+ extra cores.
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+ SMP support requires another sub-node with compatible
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+ property "brcm,bcm4708-sysram".
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+
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+Example:
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+
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+ sysram@ffff0000 {
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+ compatible = "mmio-sram";
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+ reg = <0xffff0000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0xffff0000 0x10000>;
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+
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+ smp-sysram@0 {
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+ compatible = "brcm,bcm4708-sysram";
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+ reg = <0x0 0x1000>;
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+ };
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+ };
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diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
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index 6aa331d..3507ae3 100644
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--- a/Documentation/devicetree/bindings/arm/cpus.txt
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+++ b/Documentation/devicetree/bindings/arm/cpus.txt
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@@ -188,6 +188,7 @@ nodes to be present and contain the properties described below.
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can be one of:
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"allwinner,sun6i-a31"
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"arm,psci"
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+ "brcm,bcm4708-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
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index 31141e8..c0af5cc 100644
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--- a/arch/arm/boot/dts/bcm4708.dtsi
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+++ b/arch/arm/boot/dts/bcm4708.dtsi
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@@ -15,6 +15,7 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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+ enable-method = "brcm,bcm4708-smp";
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cpu@0 {
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device_type = "cpu";
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@@ -31,4 +32,16 @@
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};
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};
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+ sysram@ffff0000 {
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+ compatible = "mmio-sram";
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+ reg = <0xffff0000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0xffff0000 0x10000>;
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+
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+ smp-sysram@0 {
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+ compatible = "brcm,bcm4708-sysram";
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+ reg = <0x0 0x1000>;
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+ };
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+ };
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};
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diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
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index 4c38674..ca12727 100644
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--- a/arch/arm/mach-bcm/Makefile
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+++ b/arch/arm/mach-bcm/Makefile
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@@ -33,6 +33,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
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# BCM5301X
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obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
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+ifeq ($(CONFIG_SMP),y)
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+obj-$(CONFIG_ARCH_BCM_5301X) += bcm5301x_smp.o bcm5301x_headsmp.o
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+endif
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# BCM63XXx
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obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
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diff --git a/arch/arm/mach-bcm/bcm5301x_headsmp.S b/arch/arm/mach-bcm/bcm5301x_headsmp.S
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new file mode 100644
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index 0000000..9ca8d20
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--- /dev/null
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+++ b/arch/arm/mach-bcm/bcm5301x_headsmp.S
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@@ -0,0 +1,45 @@
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+/*
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+ * Broadcom BCM470X / BCM5301X ARM platform code.
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+ *
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+ * Copyright (c) 2003 ARM Limited
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+ * All Rights Reserved
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+#include <linux/linkage.h>
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+
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+/*
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+ * BCM5301X specific entry point for secondary CPUs.
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+ */
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+ENTRY(bcm5301x_secondary_startup)
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+ mrc p15, 0, r0, c0, c0, 5
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+ and r0, r0, #15
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+ adr r4, 1f
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+ ldmia r4, {r5, r6}
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+ sub r4, r4, r5
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+ add r6, r6, r4
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+pen: ldr r7, [r6]
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+ cmp r7, r0
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+ bne pen
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+
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+ /*
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+ * In case L1 cache has unpredictable contents at power-up
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+ * clean its contents without flushing.
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+ */
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+ bl v7_invalidate_l1
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+
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+ mov r0, #0
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+ mcr p15, 0, r0, c7, c5, 0 /* Invalidate icache */
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+ dsb
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+ isb
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+
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+ /*
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+ * we've been released from the holding pen: secondary_stack
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+ * should now contain the SVC stack for this core
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+ */
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+ b secondary_startup
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+ENDPROC(bcm5301x_secondary_startup)
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+
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+ .align 2
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+1: .long .
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+ .long pen_release
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diff --git a/arch/arm/mach-bcm/bcm5301x_smp.c b/arch/arm/mach-bcm/bcm5301x_smp.c
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new file mode 100644
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index 0000000..45d7089
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--- /dev/null
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+++ b/arch/arm/mach-bcm/bcm5301x_smp.c
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@@ -0,0 +1,158 @@
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+/*
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+ * Broadcom BCM470X / BCM5301X ARM platform code.
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+ *
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+ * Copyright (C) 2002 ARM Ltd.
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+ * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <asm/cacheflush.h>
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+#include <asm/delay.h>
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+#include <asm/smp_plat.h>
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+#include <asm/smp_scu.h>
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+
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+#include <linux/clockchips.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+
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+#define SOC_ROM_LUT_OFF 0x400
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+
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+extern void bcm5301x_secondary_startup(void);
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+
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+static void __cpuinit write_pen_release(int val)
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+{
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+ pen_release = val;
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+ smp_wmb();
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+ sync_cache_w(&pen_release);
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+}
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+
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+static DEFINE_SPINLOCK(boot_lock);
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+
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+static void __init bcm5301x_smp_secondary_set_entry(void (*entry_point)(void))
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+{
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+ void __iomem *sysram_base_addr = NULL;
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+ struct device_node *node;
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+
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+ node = of_find_compatible_node(NULL, NULL, "brcm,bcm4708-sysram");
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+ if (!of_device_is_available(node))
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+ return;
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+
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+ sysram_base_addr = of_iomap(node, 0);
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+ if (!sysram_base_addr) {
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+ pr_warn("Failed to map sysram\n");
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+ return;
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+ }
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+
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+ writel(virt_to_phys(entry_point), sysram_base_addr + SOC_ROM_LUT_OFF);
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+
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+ dsb_sev(); /* Exit WFI */
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+ mb(); /* make sure write buffer is drained */
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+
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+ iounmap(sysram_base_addr);
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+}
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+
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+static void __init bcm5301x_smp_prepare_cpus(unsigned int max_cpus)
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+{
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+ void __iomem *scu_base;
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+
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+ if (!scu_a9_has_base()) {
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+ pr_warn("Unknown SCU base\n");
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+ return;
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+ }
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+
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+ scu_base = ioremap((phys_addr_t)scu_a9_get_base(), SZ_256);
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+ if (!scu_base) {
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+ pr_err("Failed to remap SCU\n");
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+ return;
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+ }
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+
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+ /* Initialise the SCU */
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+ scu_enable(scu_base);
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+
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+ /* Let CPUs know where to start */
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+ bcm5301x_smp_secondary_set_entry(bcm5301x_secondary_startup);
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+
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+ iounmap(scu_base);
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+}
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+
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+static void __cpuinit bcm5301x_smp_secondary_init(unsigned int cpu)
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+{
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+ trace_hardirqs_off();
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+
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+ /*
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+ * let the primary processor know we're out of the
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+ * pen, then head off into the C entry point
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+ */
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+ write_pen_release(-1);
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+
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+ /*
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+ * Synchronise with the boot thread.
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+ */
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+ spin_lock(&boot_lock);
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+ spin_unlock(&boot_lock);
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+}
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+
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+static int __cpuinit bcm5301x_smp_boot_secondary(unsigned int cpu,
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+ struct task_struct *idle)
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+{
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+ unsigned long timeout;
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+
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+ /*
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+ * set synchronisation state between this boot processor
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+ * and the secondary one
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+ */
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+ spin_lock(&boot_lock);
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+
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+ /*
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+ * The secondary processor is waiting to be released from
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+ * the holding pen - release it, then wait for it to flag
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+ * that it has been released by resetting pen_release.
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+ *
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+ * Note that "pen_release" is the hardware CPU ID, whereas
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+ * "cpu" is Linux's internal ID.
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+ */
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+ write_pen_release(cpu_logical_map(cpu));
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+
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+ /* Send the secondary CPU SEV */
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+ dsb_sev();
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+
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+ udelay(100);
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+
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+ /*
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+ * Send the secondary CPU a soft interrupt, thereby causing
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+ * the boot monitor to read the system wide flags register,
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+ * and branch to the address found there.
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+ */
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+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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+
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+ /*
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+ * Timeout set on purpose in jiffies so that on slow processors
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+ * that must also have low HZ it will wait longer.
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+ */
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+ timeout = jiffies + (HZ * 10);
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+ while (time_before(jiffies, timeout)) {
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+ smp_rmb();
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+ if (pen_release == -1)
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ /*
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+ * now the secondary core is starting up let it run its
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+ * calibrations, then wait for it to finish
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+ */
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+ spin_unlock(&boot_lock);
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+
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+ return pen_release != -1 ? -ENOSYS : 0;
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+}
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+
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+static struct smp_operations bcm5301x_smp_ops __initdata = {
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+ .smp_prepare_cpus = bcm5301x_smp_prepare_cpus,
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+ .smp_secondary_init = bcm5301x_smp_secondary_init,
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+ .smp_boot_secondary = bcm5301x_smp_boot_secondary,
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+};
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+
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+CPU_METHOD_OF_DECLARE(bcm5301x_smp, "brcm,bcm4708-smp",
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+ &bcm5301x_smp_ops);
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--
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1.8.4.5
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