mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 00:41:17 +00:00
6bf179b270
Switch to the mainline Lantiq PCIe PHY driver and update the vr9.dtsi
accordingly.
The Lantiq IRQ SMP support added upstream required changes to the SoC
dtsi as well.
Following changes are made to the Lantiq kernel patches:
0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch
0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch
applied upstream
0008-MIPS-lantiq-backport-old-timer-code.patch
access_ok API update because it lost it's type (which was the first)
parameter in upstream commit 96d4f267e40f95 ("Remove 'type' argument
from access_ok() function")
0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch
merged into 0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
revert upstream changes required for upstream xrx200 ethernet and
xrx200 (DSA) switch driver but breaking our driver
0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
required for our driver but dropped upstream, add former upstream
version
0028-NET-lantiq-various-etop-fixes.patch
now has to use the phy_set_max_speed API instead of modifying
phydev->supported. Also call ltq_dma_enable_irq() in
ltq_etop_open() based on upstream commit cc973aecf0b054 ("MIPS:
lantiq: Do not enable IRQs in dma open")
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
50 lines
1.6 KiB
Diff
50 lines
1.6 KiB
Diff
From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
|
|
From: Hauke Mehrtens <hauke@hauke-m.de>
|
|
Date: Fri, 6 Jan 2017 17:40:12 +0100
|
|
Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
|
|
|
|
This adds code to initialize the USB controller and PHY also on Danube,
|
|
Amazon SE and AR10. This code is based on the Vendor driver from
|
|
different UGW versions and compared to the hardware documentation.
|
|
|
|
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
|
---
|
|
arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
|
|
2 files changed, 110 insertions(+), 30 deletions(-)
|
|
|
|
|
|
--- a/arch/mips/lantiq/xway/sysctrl.c
|
|
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
|
@@ -244,6 +244,25 @@ static void pmu_disable(struct clk *clk)
|
|
pr_warn("deactivating PMU module failed!");
|
|
}
|
|
|
|
+static void usb_set_clock(void)
|
|
+{
|
|
+ unsigned int val = ltq_cgu_r32(ifccr);
|
|
+
|
|
+ if (of_machine_is_compatible("lantiq,ar10") ||
|
|
+ of_machine_is_compatible("lantiq,grx390")) {
|
|
+ val &= ~0x03; /* XTAL divided by 3 */
|
|
+ } else if (of_machine_is_compatible("lantiq,ar9") ||
|
|
+ of_machine_is_compatible("lantiq,vr9")) {
|
|
+ /* TODO: this depends on the XTAL frequency */
|
|
+ val |= 0x03; /* XTAL divided by 3 */
|
|
+ } else if (of_machine_is_compatible("lantiq,ase")) {
|
|
+ val |= 0x20; /* from XTAL */
|
|
+ } else if (of_machine_is_compatible("lantiq,danube")) {
|
|
+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
|
|
+ }
|
|
+ ltq_cgu_w32(val, ifccr);
|
|
+}
|
|
+
|
|
/* the pci enable helper */
|
|
static int pci_enable(struct clk *clk)
|
|
{
|
|
@@ -565,4 +584,5 @@ void __init ltq_soc_init(void)
|
|
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
|
|
clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
|
|
}
|
|
+ usb_set_clock();
|
|
}
|