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https://github.com/openwrt/openwrt.git
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6bf179b270
Switch to the mainline Lantiq PCIe PHY driver and update the vr9.dtsi
accordingly.
The Lantiq IRQ SMP support added upstream required changes to the SoC
dtsi as well.
Following changes are made to the Lantiq kernel patches:
0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch
0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch
applied upstream
0008-MIPS-lantiq-backport-old-timer-code.patch
access_ok API update because it lost it's type (which was the first)
parameter in upstream commit 96d4f267e40f95 ("Remove 'type' argument
from access_ok() function")
0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch
merged into 0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
revert upstream changes required for upstream xrx200 ethernet and
xrx200 (DSA) switch driver but breaking our driver
0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
required for our driver but dropped upstream, add former upstream
version
0028-NET-lantiq-various-etop-fixes.patch
now has to use the phy_set_max_speed API instead of modifying
phydev->supported. Also call ltq_dma_enable_irq() in
ltq_etop_open() based on upstream commit cc973aecf0b054 ("MIPS:
lantiq: Do not enable IRQs in dma open")
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
353 lines
10 KiB
Diff
353 lines
10 KiB
Diff
From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Sun, 7 Jul 2019 21:48:56 +0200
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Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
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Upstream, the GPHY Firmware loader has been merged into the DSA switch
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driver. But we don't use the driver yet, so bring it back.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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.../bindings/mips/lantiq/rcu-gphy.txt | 36 +++
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.../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++
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arch/mips/configs/xway_defconfig | 1 +
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arch/mips/lantiq/Kconfig | 4 +
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drivers/soc/lantiq/Makefile | 1 +
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drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++
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6 files changed, 284 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
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create mode 100644 drivers/soc/lantiq/gphy.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
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@@ -0,0 +1,37 @@
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+Lantiq XWAY SoC GPHY binding
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+============================
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+
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+This binding describes a software-defined ethernet PHY, provided by the RCU
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+module on newer Lantiq XWAY SoCs (xRX200 and newer).
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+
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+-------------------------------------------------------------------------------
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+Required properties:
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+- compatible : Should be one of
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+ "lantiq,xrx200-gphy"
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+ "lantiq,xrx200a1x-gphy"
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+ "lantiq,xrx200a2x-gphy"
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+ "lantiq,xrx300-gphy"
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+ "lantiq,xrx330-gphy"
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+- reg : Addrress of the GPHY FW load address register
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+- resets : Must reference the RCU GPHY reset bit
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+- reset-names : One entry, value must be "gphy" or optional "gphy2"
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+- clocks : A reference to the (PMU) GPHY clock gate
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+
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+Optional properties:
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+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
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+ <dt-bindings/mips/lantiq_xway_gphy.h>
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+
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+
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+-------------------------------------------------------------------------------
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+Example for the GPHys on the xRX200 SoCs:
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+
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+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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+ gphy0: gphy@20 {
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+ compatible = "lantiq,xrx200a2x-gphy";
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+ reg = <0x20 0x4>;
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+
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+ resets = <&reset0 31 30>, <&reset1 7 7>;
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+ reset-names = "gphy", "gphy2";
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+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
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+ lantiq,gphy-mode = <GPHY_MODE_GE>;
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+ };
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--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
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+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
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@@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
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ranges = <0x0 0x203000 0x100>;
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big-endian;
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+ gphy0: gphy@20 {
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+ compatible = "lantiq,xrx200a2x-gphy";
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+ reg = <0x20 0x4>;
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+
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+ resets = <&reset0 31 30>, <&reset1 7 7>;
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+ reset-names = "gphy", "gphy2";
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+ lantiq,gphy-mode = <GPHY_MODE_GE>;
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+ };
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+
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+ gphy1: gphy@68 {
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+ compatible = "lantiq,xrx200a2x-gphy";
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+ reg = <0x68 0x4>;
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+
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+ resets = <&reset0 29 28>, <&reset1 6 6>;
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+ reset-names = "gphy", "gphy2";
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+ lantiq,gphy-mode = <GPHY_MODE_GE>;
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+ };
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+
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reset0: reset-controller@10 {
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compatible = "lantiq,xrx200-reset";
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reg = <0x10 4>, <0x14 4>;
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--- a/arch/mips/configs/xway_defconfig
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+++ b/arch/mips/configs/xway_defconfig
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@@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
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# CONFIG_COMPAT_BRK is not set
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CONFIG_LANTIQ=y
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CONFIG_PCI_LANTIQ=y
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+CONFIG_XRX200_PHY_FW=y
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_MIPS_VPE_LOADER=y
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CONFIG_NR_CPUS=2
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--- a/arch/mips/lantiq/Kconfig
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+++ b/arch/mips/lantiq/Kconfig
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@@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
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depends on PCIE_LANTIQ && PCI_MSI
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default y
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+config XRX200_PHY_FW
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+ bool "XRX200 PHY firmware loader"
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+ depends on SOC_XWAY
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+
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endif
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--- a/drivers/soc/lantiq/Makefile
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+++ b/drivers/soc/lantiq/Makefile
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@@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y += fpi-bus.o
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+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
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--- /dev/null
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+++ b/drivers/soc/lantiq/gphy.c
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@@ -0,0 +1,235 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
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+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/firmware.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/module.h>
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+#include <linux/reboot.h>
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+#include <linux/regmap.h>
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+#include <linux/reset.h>
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+#include <linux/of_device.h>
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+#include <linux/of_platform.h>
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+#include <linux/property.h>
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+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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+
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+#include <lantiq_soc.h>
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+
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+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
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+
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+struct xway_gphy_priv {
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+ struct clk *gphy_clk_gate;
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+ struct reset_control *gphy_reset;
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+ struct reset_control *gphy_reset2;
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+ void __iomem *membase;
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+ char *fw_name;
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+};
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+
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+struct xway_gphy_match_data {
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+ char *fe_firmware_name;
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+ char *ge_firmware_name;
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+};
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+
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+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
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+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
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+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
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+};
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+
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+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
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+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
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+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
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+};
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+
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+static const struct xway_gphy_match_data xrx300_gphy_data = {
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+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
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+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
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+};
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+
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+static const struct of_device_id xway_gphy_match[] = {
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+ { .compatible = "lantiq,xrx200-gphy", .data = NULL },
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+ { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
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+ { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
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+ { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
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+ { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, xway_gphy_match);
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+
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+static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
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+ dma_addr_t *dev_addr)
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+{
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+ const struct firmware *fw;
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+ void *fw_addr;
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+ dma_addr_t dma_addr;
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+ size_t size;
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+ int ret;
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+
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+ ret = request_firmware(&fw, priv->fw_name, dev);
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+ if (ret) {
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+ dev_err(dev, "failed to load firmware: %s, error: %i\n",
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+ priv->fw_name, ret);
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+ return ret;
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+ }
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+
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+ /*
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+ * GPHY cores need the firmware code in a persistent and contiguous
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+ * memory area with a 16 kB boundary aligned start address.
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+ */
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+ size = fw->size + XRX200_GPHY_FW_ALIGN;
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+
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+ fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
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+ if (fw_addr) {
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+ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
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+ *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
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+ memcpy(fw_addr, fw->data, fw->size);
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+ } else {
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+ dev_err(dev, "failed to alloc firmware memory\n");
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+ ret = -ENOMEM;
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+ }
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+
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+ release_firmware(fw);
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+
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+ return ret;
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+}
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+
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+static int xway_gphy_of_probe(struct platform_device *pdev,
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+ struct xway_gphy_priv *priv)
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+{
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+ struct device *dev = &pdev->dev;
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+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
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+ u32 gphy_mode;
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+ int ret;
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+ struct resource *res_gphy;
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+
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+ gphy_fw_name_cfg = of_device_get_match_data(dev);
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+
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+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
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+ switch (ltq_soc_type()) {
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+ case SOC_TYPE_VR9:
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+ gphy_fw_name_cfg = &xrx200a1x_gphy_data;
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+ break;
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+ case SOC_TYPE_VR9_2:
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+ gphy_fw_name_cfg = &xrx200a2x_gphy_data;
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+ break;
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+ }
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+
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+ priv->gphy_clk_gate = devm_clk_get(dev, NULL);
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+ if (IS_ERR(priv->gphy_clk_gate)) {
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+ dev_err(dev, "Failed to lookup gate clock\n");
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+ return PTR_ERR(priv->gphy_clk_gate);
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+ }
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+
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+ res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ priv->membase = devm_ioremap_resource(dev, res_gphy);
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+ if (IS_ERR(priv->membase))
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+ return PTR_ERR(priv->membase);
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+
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+ priv->gphy_reset = devm_reset_control_get(dev, "gphy");
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+ if (IS_ERR(priv->gphy_reset)) {
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+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
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+ dev_err(dev, "Failed to lookup gphy reset\n");
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+ return PTR_ERR(priv->gphy_reset);
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+ }
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+
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+ priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
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+ if (IS_ERR(priv->gphy_reset2))
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+ return PTR_ERR(priv->gphy_reset2);
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+
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+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
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+ /* Default to GE mode */
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+ if (ret)
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+ gphy_mode = GPHY_MODE_GE;
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+
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+ switch (gphy_mode) {
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+ case GPHY_MODE_FE:
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+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
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+ break;
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+ case GPHY_MODE_GE:
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+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
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+ break;
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+ default:
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+ dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int xway_gphy_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct xway_gphy_priv *priv;
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+ dma_addr_t fw_addr = 0;
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+ int ret;
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+
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+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ ret = xway_gphy_of_probe(pdev, priv);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_prepare_enable(priv->gphy_clk_gate);
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+ if (ret)
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+ return ret;
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+
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+ ret = xway_gphy_load(dev, priv, &fw_addr);
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+ if (ret) {
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+ clk_disable_unprepare(priv->gphy_clk_gate);
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+ return ret;
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+ }
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+
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+ reset_control_assert(priv->gphy_reset);
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+ reset_control_assert(priv->gphy_reset2);
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+
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+ iowrite32be(fw_addr, priv->membase);
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+
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+ reset_control_deassert(priv->gphy_reset);
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+ reset_control_deassert(priv->gphy_reset2);
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+
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+ platform_set_drvdata(pdev, priv);
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+
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+ return ret;
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+}
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+
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+static int xway_gphy_remove(struct platform_device *pdev)
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+{
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+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
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+
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+ iowrite32be(0, priv->membase);
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+
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+ clk_disable_unprepare(priv->gphy_clk_gate);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver xway_gphy_driver = {
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+ .probe = xway_gphy_probe,
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+ .remove = xway_gphy_remove,
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+ .driver = {
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+ .name = "xway-rcu-gphy",
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+ .of_match_table = xway_gphy_match,
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+ },
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+};
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+
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+module_platform_driver(xway_gphy_driver);
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+
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+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
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+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
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+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
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+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
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+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
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+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
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+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
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+MODULE_LICENSE("GPL");
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