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0806f8fc80
Following changes are made to the Lantiq kernel patches:
0001-MIPS-lantiq-add-pcie-driver.patch
The pci header isn't included by the of_pci header any longer
0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
Due to the merge of grx390 and ar10 clocks, extend support to grx390
0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch
The do_carrier arguments was dropped from phy_link_change. The
phylib has always sets the third parameter to true so the flag is
always changed anyway.
of_get_phy_mode() returns an error, or 0 on success, and pass a
pointer, of type phy_interface_t, where the phy mode should be
stored now. So far an error wasn't considered. Print at least an
error message if something unexpected happens.
The stuck queue is now passed to xrx200_tx_timeout (the timeout
handler) but not used so far.
0028-NET-lantiq-various-etop-fixes.patch
ioremap has provided non-cached semantics by default since the Linux
2.6 days and was removed with kernel version 5.6.
of_get_phy_mode() returns an error, or 0 on success, and pass a
pointer, of type phy_interface_t, where the phy mode should be
stored now. So far an error wasn't considered. Print at least an
error message if something unexpected happens.
0042-arch-mips-increase-io_space_limit.patch
Move IO space extension to laniq specific file
Signed-off-by: Mathias Kresin <dev@kresin.me>
122 lines
3.7 KiB
Diff
122 lines
3.7 KiB
Diff
From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 9 Sep 2014 23:12:15 +0200
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Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 63 insertions(+)
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--- a/drivers/mtd/nand/raw/xway_nand.c
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+++ b/drivers/mtd/nand/raw/xway_nand.c
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@@ -61,6 +61,24 @@
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#define NAND_CON_CSMUX (1 << 1)
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#define NAND_CON_NANDM 1
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+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr))
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+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400)
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+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080)
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+
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+/*
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+ * req_mask provides a mechanism to prevent interference between
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+ * nand and pci (probably only relevant for the BT Home Hub 2B).
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+ * Setting it causes the corresponding pci req pins to be masked
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+ * during nand access, and also moves ebu locking from the read/write
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+ * functions to the chip select function to ensure that the whole
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+ * operation runs with interrupts disabled.
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+ * In addition it switches on some extra waiting in xway_cmd_ctrl().
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+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
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+ * which in turn seems to be necessary for the nor chip to be recognised
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+ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
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+ */
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+static __be32 req_mask = 0;
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+
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struct xway_nand_data {
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struct nand_controller controller;
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struct nand_chip chip;
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@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand
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case -1:
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ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
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ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
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+
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+ if (req_mask) {
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+ /* Unmask all external PCI request */
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+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
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+ }
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+
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spin_unlock_irqrestore(&ebu_lock, data->csflags);
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break;
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case 0:
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spin_lock_irqsave(&ebu_lock, data->csflags);
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+
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+ if (req_mask) {
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+ /* Mask all external PCI request */
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+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
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+ }
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+
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ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
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ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
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break;
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@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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+ if (req_mask) {
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+ if (cmd != NAND_CMD_STATUS)
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+ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
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+ }
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+
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if (cmd == NAND_CMD_NONE)
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return;
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@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch
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while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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;
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+
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+ if (req_mask) {
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+ /*
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+ * program and erase have their own busy handlers
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+ * status and sequential in needs no delay
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+ */
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+ switch (cmd) {
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+ case NAND_CMD_ERASE1:
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+ case NAND_CMD_SEQIN:
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+ case NAND_CMD_STATUS:
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+ case NAND_CMD_READID:
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+ return;
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+ }
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+
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+ /* wait until command is processed */
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+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
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+ ;
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+ }
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}
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static int xway_dev_ready(struct nand_chip *chip)
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@@ -171,6 +224,7 @@ static int xway_nand_probe(struct platfo
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int err;
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u32 cs;
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u32 cs_flag = 0;
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+ const __be32 *req_mask_ptr;
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/* Allocate memory for the device structure (and zero it) */
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data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
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@@ -207,6 +261,15 @@ static int xway_nand_probe(struct platfo
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if (!err && cs == 1)
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cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
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+ req_mask_ptr = of_get_property(pdev->dev.of_node,
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+ "req-mask", NULL);
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+
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+ /*
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+ * Load the PCI req lines to mask from the device tree. If the
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+ * property is not present, setting req_mask to 0 disables masking.
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+ */
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+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
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+
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/* setup the EBU to run in NAND mode on our base addr */
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ltq_ebu_w32(CPHYSADDR(data->nandaddr)
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| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
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