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205 lines
6.3 KiB
Diff
205 lines
6.3 KiB
Diff
From 257d5fe12600f08df764cac0abc17bef7b6fae9b Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 19 Jun 2011 17:51:30 +0200
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Subject: [PATCH 07/14] bcma: get CPU clock
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Add method to return the clock of the CPU. This is needed by the arch
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code to calculate the mips_hpt_frequency.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/bcma/bcma_private.h | 3 +
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drivers/bcma/driver_chipcommon_pmu.c | 87 +++++++++++++++++++++++++++
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drivers/bcma/driver_mips.c | 12 ++++
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include/linux/bcma/bcma_driver_chipcommon.h | 35 +++++++++++
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include/linux/bcma/bcma_driver_mips.h | 1 +
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5 files changed, 138 insertions(+), 0 deletions(-)
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -29,6 +29,9 @@ void bcma_init_bus(struct bcma_bus *bus)
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/* sprom.c */
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int bcma_sprom_get(struct bcma_bus *bus);
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+/* driver_chipcommon_pmu.c */
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+extern u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
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+
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/* driver_chipcommon.c */
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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extern int bcma_chipco_serial_init(struct bcma_drv_cc *cc,
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--- a/drivers/bcma/driver_chipcommon_pmu.c
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+++ b/drivers/bcma/driver_chipcommon_pmu.c
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@@ -11,6 +11,13 @@
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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+static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
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+{
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+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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+ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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+ return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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+}
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+
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static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set)
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{
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@@ -136,3 +143,83 @@ void bcma_pmu_init(struct bcma_drv_cc *c
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bcma_pmu_swreg_init(cc);
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bcma_pmu_workarounds(cc);
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}
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+
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+static u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+
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+ switch (bus->chipinfo.id) {
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+ case 0x4716:
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+ case 0x4748:
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+ case 47162:
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+ /* always 20Mhz */
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+ return 20000 * 1000;
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+ default:
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+ pr_warn("No ALP clock specified for %04X device, "
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+ "pmu rev. %d, using default %d Hz\n",
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+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
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+ }
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+ return BCMA_CC_PMU_ALP_CLOCK;
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+}
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+
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+/* Find the output of the "m" pll divider given pll controls that start with
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+ * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
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+ */
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+static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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+{
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+ u32 tmp, div, ndiv, p1, p2, fc;
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+
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+ BUG_ON(!m || m > 4);
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+
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+ BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
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+
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+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
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+ p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
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+ p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
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+
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+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
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+ div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
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+ BCMA_CC_PPL_MDIV_MASK;
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+
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+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
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+ ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
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+
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+ /* Do calculation in Mhz */
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+ fc = bcma_pmu_alp_clock(cc) / 1000000;
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+ fc = (p1 * ndiv * fc) / p2;
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+
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+ /* Return clock in Hertz */
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+ return (fc / div) * 1000000;
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+}
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+
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+/* query bus clock frequency for PMU-enabled chipcommon */
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+u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+
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+ switch (bus->chipinfo.id) {
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+ case 0x4716:
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+ case 0x4748:
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+ case 47162:
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+ return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
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+ BCMA_CC_PMU5_MAINPLL_SSB);
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+ default:
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+ pr_warn("No backplane clock specified for %04X device, "
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+ "pmu rev. %d, using default %d Hz\n",
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+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
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+ }
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+ return BCMA_CC_PMU_HT_CLOCK;
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+}
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+
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+/* query cpu clock frequency for PMU-enabled chipcommon */
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+u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+
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+ if ((cc->pmu.rev == 5 || cc->pmu.rev == 6 || cc->pmu.rev == 7) &&
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+ (bus->chipinfo.id != 0x4319))
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+ return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
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+ BCMA_CC_PMU5_MAINPLL_CPU);
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+
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+ return bcma_pmu_get_clockcontrol(cc);
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+}
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--- a/drivers/bcma/driver_mips.c
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+++ b/drivers/bcma/driver_mips.c
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@@ -157,6 +157,18 @@ static void bcma_core_mips_dump_irq(stru
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}
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}
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+u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
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+{
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+ struct bcma_bus *bus = mcore->core->bus;
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+
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+ if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
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+ return bcma_pmu_get_clockcpu(&bus->drv_cc);
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+
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+ pr_err("No PMU available, need this to get the cpu clock\n");
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+ return 0;
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+}
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+EXPORT_SYMBOL(bcma_cpu_clock);
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+
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static void bcma_core_mips_serial_init(struct bcma_drv_mips *mcore)
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{
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struct bcma_bus *bus = mcore->core->bus;
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -246,6 +246,41 @@
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#define BCMA_CC_PLLCTL_DATA 0x0664
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#define BCMA_CC_SPROM 0x0830 /* SPROM beginning */
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+/* Divider allocation in 4716/47162/5356 */
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+#define BCMA_CC_PMU5_MAINPLL_CPU 1
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+#define BCMA_CC_PMU5_MAINPLL_MEM 2
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+#define BCMA_CC_PMU5_MAINPLL_SSB 3
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+
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+/* PLL usage in 4716/47162 */
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+#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
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+
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+/* ALP clock on pre-PMU chips */
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+#define BCMA_CC_PMU_ALP_CLOCK 20000000
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+/* HT clock for systems with PMU-enabled chipcommon */
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+#define BCMA_CC_PMU_HT_CLOCK 80000000
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+
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+/* PMU rev 5 (& 6) */
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+#define BCMA_CC_PPL_P1P2_OFF 0
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+#define BCMA_CC_PPL_P1_MASK 0x0f000000
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+#define BCMA_CC_PPL_P1_SHIFT 24
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+#define BCMA_CC_PPL_P2_MASK 0x00f00000
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+#define BCMA_CC_PPL_P2_SHIFT 20
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+#define BCMA_CC_PPL_M14_OFF 1
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+#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
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+#define BCMA_CC_PPL_MDIV_WIDTH 8
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+#define BCMA_CC_PPL_NM5_OFF 2
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+#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
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+#define BCMA_CC_PPL_NDIV_SHIFT 20
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+#define BCMA_CC_PPL_FMAB_OFF 3
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+#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
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+#define BCMA_CC_PPL_MRAT_SHIFT 28
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+#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
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+#define BCMA_CC_PPL_ABRAT_SHIFT 27
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+#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
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+#define BCMA_CC_PPL_PLLCTL_OFF 4
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+#define BCMA_CC_PPL_PCHI_OFF 5
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+#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
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+
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/* Data for the PMU, if available.
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* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
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*/
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--- a/include/linux/bcma/bcma_driver_mips.h
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+++ b/include/linux/bcma/bcma_driver_mips.h
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@@ -54,6 +54,7 @@ struct bcma_drv_mips {
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};
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extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
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+extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
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extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
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