openwrt/target/linux/ath79/dts/ar7241_ubnt_xm.dtsi
Mathias Kresin 0ff5785c5d ath79: fix dts files
Add the SoC compatible to the individual dts files. Rename the dts files
to match the common pattern.

Remove dts files wich aren't used and no image in ar71xx exists.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-05-17 07:40:19 +02:00

154 lines
2.2 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ar7241.dtsi"
/ {
compatible = "ubnt,xm", "qca,ar7241";
model = "Ubiquiti Networks XM (rev 1.0) board";
memory@0 {
device_type = "memory";
reg = <0x0 0x2000000>;
};
/* extosc: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
*/
keys {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <20>;
button@0 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
led@0 {
label = "ubnt:red:link1";
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
};
led@1 {
label = "ubnt:orange:link2";
gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};
led@2 {
label = "ubnt:green:link3";
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
};
led@3 {
label = "ubnt:green:link4";
gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
};
};
};
&uart {
status = "okay";
};
/*&pll {
clocks = <&extosc>;
};*/
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l6405d";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x040000>;
read-only;
};
partition@1 {
label = "u-boot-env";
reg = <0x040000 0x010000>;
};
partition@2 {
label = "firmware";
reg = <0x050000 0x750000>;
};
partition@3 {
label = "board_config";
reg = <0x7a0000 0x010000>;
read-only;
};
partition@4 {
label = "cfg";
reg = <0x7b0000 0x040000>;
read-only;
};
art: partition@5 {
label = "art";
reg = <0x7f0000 0x010000>;
read-only;
};
};
};
};
&pcie {
status = "okay";
ath9k@0000 {
reg = <0x0000 0 0 0 0>;
qca,no-eeprom;
};
};
&mdio0 {
status = "okay";
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "mii";
};
};
&eth0 {
status = "okay";
mtd-mac-address = <&art 0x0>;
phy-mode = "mii";
phy-handle = <&phy4>;
};
&eth1 {
status = "okay";
mtd-mac-address = <&art 0x6>;
};