mirror of
https://github.com/openwrt/openwrt.git
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24d84a13a4
Manually rebased:
ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch
All other patches automatically rebased.
Signed-off-by: John Audia <therealgraysky@proton.me>
(cherry picked from commit d4aad642ff)
143 lines
4.5 KiB
Diff
143 lines
4.5 KiB
Diff
From b1388530046be8a912979594f9c43b47d6f242fe Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 8 Oct 2020 16:06:58 +0200
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Subject: [PATCH] drm/vc4: hdmi: Enable the scrambler
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The HDMI controller on the BCM2711 includes a scrambler in order to
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reach the HDMI 2.0 modes that require it. Let's add the support for it.
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Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 64 +++++++++++++++++++++++++++++
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drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 ++
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2 files changed, 67 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -35,6 +35,7 @@
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#include <drm/drm_edid.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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+#include <drm/drm_scdc_helper.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/i2c.h>
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@@ -77,6 +78,8 @@
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#define VC5_HDMI_VERTB_VSPO_SHIFT 16
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#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
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+#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
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+
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#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
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#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
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@@ -520,6 +523,64 @@ static void vc4_hdmi_set_infoframes(stru
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vc4_hdmi_set_hdr_infoframe(encoder);
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}
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+static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
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+ struct drm_display_mode *mode)
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+{
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+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
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+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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+ struct drm_display_info *display = &vc4_hdmi->connector.display_info;
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+
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+ if (!vc4_encoder->hdmi_monitor)
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+ return false;
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+
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+ if (!display->hdmi.scdc.supported ||
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+ !display->hdmi.scdc.scrambling.supported)
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+ return false;
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+
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+ return true;
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+}
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+
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+static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
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+{
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+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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+
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+ if (!vc4_hdmi_supports_scrambling(encoder, mode))
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+ return;
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+
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+ if (!vc4_hdmi_mode_needs_scrambling(mode))
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+ return;
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+
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+ drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
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+ drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
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+
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+ HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
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+ VC5_HDMI_SCRAMBLER_CTL_ENABLE);
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+}
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+
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+static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
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+{
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+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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+ struct drm_crtc *crtc = encoder->crtc;
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+
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+ /*
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+ * At boot, encoder->crtc will be NULL. Since we don't know the
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+ * state of the scrambler and in order to avoid any
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+ * inconsistency, let's disable it all the time.
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+ */
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+ if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
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+ return;
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+
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+ if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
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+ return;
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+
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+ HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
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+ ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
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+
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+ drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
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+ drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
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+}
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+
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static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
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struct drm_atomic_state *state)
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{
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@@ -532,6 +593,8 @@ static void vc4_hdmi_encoder_post_crtc_d
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HDMI_WRITE(HDMI_VID_CTL,
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HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
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+
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+ vc4_hdmi_disable_scrambling(encoder);
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}
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static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
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@@ -983,6 +1046,7 @@ static void vc4_hdmi_encoder_post_crtc_e
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}
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vc4_hdmi_recenter_fifo(vc4_hdmi);
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+ vc4_hdmi_enable_scrambling(encoder);
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}
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static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
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@@ -100,6 +100,7 @@ enum vc4_hdmi_field {
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HDMI_RM_FORMAT,
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HDMI_RM_OFFSET,
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HDMI_SCHEDULER_CONTROL,
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+ HDMI_SCRAMBLER_CTL,
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HDMI_SW_RESET_CONTROL,
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HDMI_TX_PHY_CHANNEL_SWAP,
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HDMI_TX_PHY_CLK_DIV,
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@@ -238,6 +239,7 @@ static const struct vc4_hdmi_register vc
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VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
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VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
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VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
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+ VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
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VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
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VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
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@@ -317,6 +319,7 @@ static const struct vc4_hdmi_register vc
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VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
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VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
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VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
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+ VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
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VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
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VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
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