mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-19 13:48:06 +00:00
467b07e00c
Refreshed all patches Compile-tested on: cns3xxx, imx6, x86_64 Runtime-tested on: cns3xxx, imx6, x86_64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Michael Yartys <michael.yartys@protonmail.com>
96 lines
2.8 KiB
Diff
96 lines
2.8 KiB
Diff
From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
|
|
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
|
Date: Tue, 19 Jul 2016 18:44:49 +0530
|
|
Subject: PCI: qcom: Fixed IPQ806x specific clocks
|
|
|
|
Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
|
|
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
|
---
|
|
drivers/pci/host/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++++-----
|
|
1 file changed, 33 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/pci/dwc/pcie-qcom.c
|
|
+++ b/drivers/pci/dwc/pcie-qcom.c
|
|
@@ -91,6 +91,8 @@ struct qcom_pcie_resources_2_1_0 {
|
|
struct clk *iface_clk;
|
|
struct clk *core_clk;
|
|
struct clk *phy_clk;
|
|
+ struct clk *aux_clk;
|
|
+ struct clk *ref_clk;
|
|
struct reset_control *pci_reset;
|
|
struct reset_control *axi_reset;
|
|
struct reset_control *ahb_reset;
|
|
@@ -249,6 +251,14 @@ static int qcom_pcie_get_resources_2_1_0
|
|
if (IS_ERR(res->phy_clk))
|
|
return PTR_ERR(res->phy_clk);
|
|
|
|
+ res->aux_clk = devm_clk_get(dev, "aux");
|
|
+ if (IS_ERR(res->aux_clk))
|
|
+ return PTR_ERR(res->aux_clk);
|
|
+
|
|
+ res->ref_clk = devm_clk_get(dev, "ref");
|
|
+ if (IS_ERR(res->ref_clk))
|
|
+ return PTR_ERR(res->ref_clk);
|
|
+
|
|
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
|
|
if (IS_ERR(res->pci_reset))
|
|
return PTR_ERR(res->pci_reset);
|
|
@@ -281,6 +291,8 @@ static void qcom_pcie_deinit_2_1_0(struc
|
|
clk_disable_unprepare(res->iface_clk);
|
|
clk_disable_unprepare(res->core_clk);
|
|
clk_disable_unprepare(res->phy_clk);
|
|
+ clk_disable_unprepare(res->aux_clk);
|
|
+ clk_disable_unprepare(res->ref_clk);
|
|
regulator_disable(res->vdda);
|
|
regulator_disable(res->vdda_phy);
|
|
regulator_disable(res->vdda_refclk);
|
|
@@ -324,16 +336,28 @@ static int qcom_pcie_init_2_1_0(struct q
|
|
goto err_assert_ahb;
|
|
}
|
|
|
|
+ ret = clk_prepare_enable(res->core_clk);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "cannot prepare/enable core clock\n");
|
|
+ goto err_clk_core;
|
|
+ }
|
|
+
|
|
ret = clk_prepare_enable(res->phy_clk);
|
|
if (ret) {
|
|
dev_err(dev, "cannot prepare/enable phy clock\n");
|
|
goto err_clk_phy;
|
|
}
|
|
|
|
- ret = clk_prepare_enable(res->core_clk);
|
|
+ ret = clk_prepare_enable(res->aux_clk);
|
|
if (ret) {
|
|
- dev_err(dev, "cannot prepare/enable core clock\n");
|
|
- goto err_clk_core;
|
|
+ dev_err(dev, "cannot prepare/enable aux clock\n");
|
|
+ goto err_clk_aux;
|
|
+ }
|
|
+
|
|
+ ret = clk_prepare_enable(res->ref_clk);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "cannot prepare/enable ref clock\n");
|
|
+ goto err_clk_ref;
|
|
}
|
|
|
|
ret = reset_control_deassert(res->ahb_reset);
|
|
@@ -389,10 +413,14 @@ static int qcom_pcie_init_2_1_0(struct q
|
|
return 0;
|
|
|
|
err_deassert_ahb:
|
|
- clk_disable_unprepare(res->core_clk);
|
|
-err_clk_core:
|
|
+ clk_disable_unprepare(res->ref_clk);
|
|
+err_clk_ref:
|
|
+ clk_disable_unprepare(res->aux_clk);
|
|
+err_clk_aux:
|
|
clk_disable_unprepare(res->phy_clk);
|
|
err_clk_phy:
|
|
+ clk_disable_unprepare(res->core_clk);
|
|
+err_clk_core:
|
|
clk_disable_unprepare(res->iface_clk);
|
|
err_assert_ahb:
|
|
regulator_disable(res->vdda_phy);
|