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Panasonic Switch-M24eG PN28240K is a 24 + 2 port gigabit switch, based on
RTL8382M.
Specification:
- SoC : Realtek RTL8382M
- RAM : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x24 + 2
- port 1-8 : TP, RTL8218B
- port 9-16 : TP, RTL8218B (SoC)
- port 17-24 : RTL8218FB
- port 17-22: TP
- port 23-24: TP/SFP (Combo)
- LEDs/Keys : 7x / 1x
- UART : RS-232 port on the front panel (connector: RJ-45)
- 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
- 9600n8
- Power : 100-240 VAC, 50/60 Hz, 0.5 A
- Plug : IEC 60320-C13
- Stock OS : VxWorks based
Flash instruction using initramfs image:
1. Prepare the TFTP server with the IP address 192.168.1.111
2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
the TFTP directory
3. Download the official upgrading firmware (ex: pn28240k_v30000.rom)
and place it to the TFTP directory
4. Boot M24eG and interrupt the U-Boot with Ctrl + C keys
5. Execute the following commands and boot with the OpenWrt initramfs
image
rtk network on
tftpboot 0x81000000
bootm
6. Backup mtdblock files to the computer by scp or anything and reboot
7. Interrupt the U-Boot and execute the following commands to re-create
filesystem in the flash
ffsmount c:/
ffsfmt c:/
this step takes a long time, about ~ 4 mins
8. Execute the following commands to put the official images to the
filesystem
updatert <official image>
example:
updatert pn28240k_v30000.rom
this step takes about ~ 40 secs
9. Set the environment variables of the U-Boot by the following commands
setenv loadaddr 0xb4e00000
setenv bootcmd bootm
saveenv
10: Download the OpenWrt initramfs image and boot with it
tftpboot 0x81000000 0101A8C0.img
bootm
11: On the initramfs image, download the sysupgrade image and perform
sysupgrade with it
sysupgrade <imagename>
12: Wait ~ 120 seconds to complete flashing
Known Issues:
- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
phy driver has no support for it. Currently, only TP ports work by the
RTL8218D support.
Note:
- "Switch-M24eG" is a model name, and "PN28240K" is a model number.
Switch-M24eG has an another (old) model number ("PN28240"), it's not a
Realtek based hardware.
- Switch-M24eG has a "POWER" LED (Green), but it's not connected to any
GPIO pin.
- U-Boot checks the runtime images in the flash when booting and fails
to execute "bootcmd" variable if the images are not existing.
- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
firmware and it includes the stock images, configuration files and
checksum files. It's unknown format, can't be managed on the OpenWrt.
To get the enough space for OpenWrt, move the filesystem to the head
of "fs_reserved" partition by execution of "ffsfmt" and "updatert".
- A GPIO pin on PCA9539 is used for resetting external RTL8218B phy and
RTL8218FB phy.
This should be specified as "reset-gpios" property in MDIO node, but
the current configuration of RTL8218B phy in the phy driver seems to
be incomplete and RTL8218FB won't be configured on RTL8218D support.
So, ethernet ports on these phys will be broken after hard-resetting.
At the moment, configure this pin as gpio-hog to avoid breaking by
resetting.
Back to the stock firmware:
1. Delete "loadaddr" variable and set "bootcmd" to the original value
on U-Boot:
setenv loadaddr
setenv bootcmd 'bootm 0x81000000'
on OpenWrt:
fw_setenv loadaddr
fw_setenv bootcmd 'bootm 0x81000000'
2. Perform reset or reboot
on U-Boot:
reset
on OpenWrt:
reboot
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
191 lines
4.2 KiB
Plaintext
191 lines
4.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "panasonic,m24eg-pn28240k", "realtek,rtl8382-soc";
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model = "Panasonic Switch-M24eG PN28240K";
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aliases {
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led-boot = &led_status_eco_green;
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led-failsafe = &led_status_eco_amber;
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led-running = &led_status_eco_green;
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led-upgrade = &led_status_eco_green;
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};
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/*
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* sfp0/1 are "combo" port with each TP port (23/24), and they are
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* connected to the RTL8218FB. Currently, there is no support for
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* the chip and only TP ports work by the RTL8218D support.
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*/
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sfp0: sfp-p23 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p24 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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};
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};
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&leds {
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led_status_eco_amber: led-5 {
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label = "amber:status_eco";
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gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <1>;
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};
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led_status_eco_green: led-6 {
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label = "green:status_eco";
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gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <2>;
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};
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};
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&i2c_gpio_0 {
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scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&i2c_gpio_1 {
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scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&gpio2 {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gpio0>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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/*
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* GPIO12 (IO1_4): RTL8218B + RTL8218FB
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*
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* This GPIO pin should be specified as "reset-gpio" in mdio node,
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* but the current configuration of RTL8218B phy in the phy driver
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* seems to be incomplete and RTL8218FB phy won't be configured on
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* RTL8218D support. So, ethernet ports on these phys will be broken
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* after hard-resetting.
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* (RTL8218FB phy will be detected as RTL8218D by the phy driver)
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* At the moment, configure this GPIO pin as gpio-hog to avoid breaking
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* by resetting.
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*/
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ext_switch_reset {
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gpio-hog;
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gpios = <12 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "ext-switch-reset";
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};
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};
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&i2c_switch {
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i2c0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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ðernet0 {
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mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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/* RTL8218FB */
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(0, 1, qsgmii)
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SWITCH_PORT(1, 2, qsgmii)
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SWITCH_PORT(2, 3, qsgmii)
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SWITCH_PORT(3, 4, qsgmii)
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SWITCH_PORT(4, 5, qsgmii)
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SWITCH_PORT(5, 6, qsgmii)
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SWITCH_PORT(6, 7, qsgmii)
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SWITCH_PORT(7, 8, qsgmii)
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SWITCH_PORT(8, 9, internal)
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SWITCH_PORT(9, 10, internal)
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SWITCH_PORT(10, 11, internal)
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SWITCH_PORT(11, 12, internal)
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SWITCH_PORT(12, 13, internal)
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SWITCH_PORT(13, 14, internal)
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SWITCH_PORT(14, 15, internal)
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SWITCH_PORT(15, 16, internal)
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SWITCH_PORT(16, 17, qsgmii)
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SWITCH_PORT(17, 18, qsgmii)
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SWITCH_PORT(18, 19, qsgmii)
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SWITCH_PORT(19, 20, qsgmii)
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SWITCH_PORT(20, 21, qsgmii)
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SWITCH_PORT(21, 22, qsgmii)
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SWITCH_PORT(22, 23, qsgmii)
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SWITCH_PORT(23, 24, qsgmii)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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