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f4b687d1f0
If _machine_hang is not defined on MIPS, the kernel will check if the CPU can enter a more power efficient sleep mode. Since the realtek platform supports mips32_r2, this should issue a WAIT instruction instead of a trivial infinite loop. Signed-off-by: Sander Vanheule <sander@svanheule.net>
103 lines
2.4 KiB
C
103 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Setup for the Realtek RTL838X SoC:
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* Memory, Timer and Serial
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*
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* Copyright (C) 2020 B. Koblitz
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* based on the original BSP by
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* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
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*
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*/
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#include <linux/console.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <linux/of_fdt.h>
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#include <asm/reboot.h>
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#include <asm/time.h> /* for mips_hpt_frequency */
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#include <asm/prom.h>
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#include <asm/smp-ops.h>
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#include "mach-rtl83xx.h"
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extern int rtl838x_serial_init(void);
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extern struct rtl83xx_soc_info soc_info;
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u32 pll_reset_value;
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static void rtl838x_restart(char *command)
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{
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u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
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/* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
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void (*f)(void) = (void *) 0xbfc00000;
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pr_info("System restart.\n");
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if (soc_info.family == RTL8390_FAMILY_ID) {
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f();
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/* If calling reset vector fails, reset entire chip */
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sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
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/* If this fails, halt the CPU */
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while
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(1);
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}
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pr_info("PLL control register: %x, applying reset value %x\n",
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pll, pll_reset_value);
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sw_w32(3, RTL838X_INT_RW_CTRL);
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sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
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sw_w32(0, RTL838X_INT_RW_CTRL);
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pr_info("Resetting RTL838X SoC\n");
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/* Reset Global Control1 Register */
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sw_w32(1, RTL838X_RST_GLB_CTRL_1);
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}
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void __init plat_mem_setup(void)
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{
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void *dtb;
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set_io_port_base(KSEG1);
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_machine_restart = rtl838x_restart;
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if (fw_passed_dtb) /* UHI interface */
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dtb = (void *)fw_passed_dtb;
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else if (__dtb_start != __dtb_end)
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dtb = (void *)__dtb_start;
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else
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panic("no dtb found");
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/*
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* Load the devicetree. This causes the chosen node to be
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* parsed resulting in our memory appearing
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*/
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__dt_setup_arch(dtb);
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}
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void __init plat_time_init(void)
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{
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struct device_node *np;
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u32 freq = 500000000;
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np = of_find_node_by_name(NULL, "cpus");
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if (!np) {
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pr_err("Missing 'cpus' DT node, using default frequency.");
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} else {
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if (of_property_read_u32(np, "frequency", &freq) < 0)
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pr_err("No 'frequency' property in DT, using default.");
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else
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pr_info("CPU frequency from device tree: %d", freq);
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of_node_put(np);
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}
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mips_hpt_frequency = freq / 2;
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pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
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}
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