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2b88563ee5
* rename the target to realtek * add refactored DSA driver * add latest gpio driver * lots of arch cleanups * new irq driver * additional boards Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: John Crispin <john@phrozen.org>
168 lines
4.3 KiB
C
168 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Realtek RTL83XX architecture specific IRQ handling
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*
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* based on the original BSP
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* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
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* Copyright (C) 2020 B. Koblitz
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* Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
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* Copyright (C) 2020 John Crispin <john@phrozen.org>
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*/
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#include <linux/irqchip.h>
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#include <linux/spinlock.h>
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#include <linux/of_address.h>
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#include <asm/irq_cpu.h>
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#include <linux/of_irq.h>
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#include <asm/cevt-r4k.h>
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#include <mach-rtl83xx.h>
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#include "irq.h"
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#define REALTEK_CPU_IRQ_SHARED0 (MIPS_CPU_IRQ_BASE + 2)
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#define REALTEK_CPU_IRQ_UART (MIPS_CPU_IRQ_BASE + 3)
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#define REALTEK_CPU_IRQ_SWITCH (MIPS_CPU_IRQ_BASE + 4)
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#define REALTEK_CPU_IRQ_SHARED1 (MIPS_CPU_IRQ_BASE + 5)
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#define REALTEK_CPU_IRQ_EXTERNAL (MIPS_CPU_IRQ_BASE + 6)
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#define REALTEK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
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#define REG(x) (rtl83xx_ictl_base + x)
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extern struct rtl83xx_soc_info soc_info;
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static DEFINE_RAW_SPINLOCK(irq_lock);
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static void __iomem *rtl83xx_ictl_base;
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static void rtl83xx_ictl_enable_irq(struct irq_data *i)
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{
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&irq_lock, flags);
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value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
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value |= BIT(i->hwirq);
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rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
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raw_spin_unlock_irqrestore(&irq_lock, flags);
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}
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static void rtl83xx_ictl_disable_irq(struct irq_data *i)
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{
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&irq_lock, flags);
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value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
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value &= ~BIT(i->hwirq);
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rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
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raw_spin_unlock_irqrestore(&irq_lock, flags);
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}
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static struct irq_chip rtl83xx_ictl_irq = {
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.name = "RTL83xx",
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.irq_enable = rtl83xx_ictl_enable_irq,
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.irq_disable = rtl83xx_ictl_disable_irq,
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.irq_ack = rtl83xx_ictl_disable_irq,
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.irq_mask = rtl83xx_ictl_disable_irq,
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.irq_unmask = rtl83xx_ictl_enable_irq,
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.irq_eoi = rtl83xx_ictl_enable_irq,
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};
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static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(hw, &rtl83xx_ictl_irq, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops irq_domain_ops = {
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.map = intc_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static void rtl838x_irq_dispatch(struct irq_desc *desc)
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{
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unsigned int pending = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)) & rtl83xx_r32(REG(RTL83XX_ICTL_GISR));
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if (pending) {
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
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} else {
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spurious_interrupt();
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending;
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pending = read_c0_cause() & read_c0_status() & ST0_IM;
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if (pending & CAUSEF_IP7)
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do_IRQ(REALTEK_CPU_IRQ_COUNTER);
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else if (pending & CAUSEF_IP6)
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do_IRQ(REALTEK_CPU_IRQ_EXTERNAL);
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else if (pending & CAUSEF_IP5)
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do_IRQ(REALTEK_CPU_IRQ_SHARED1);
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else if (pending & CAUSEF_IP4)
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do_IRQ(REALTEK_CPU_IRQ_SWITCH);
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else if (pending & CAUSEF_IP3)
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do_IRQ(REALTEK_CPU_IRQ_UART);
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else if (pending & CAUSEF_IP2)
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do_IRQ(REALTEK_CPU_IRQ_SHARED0);
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else
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spurious_interrupt();
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}
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static void __init icu_of_init(struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *domain;
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domain = irq_domain_add_simple(node, 32, 0,
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&irq_domain_ops, NULL);
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irq_set_chained_handler_and_data(2, rtl838x_irq_dispatch, domain);
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irq_set_chained_handler_and_data(5, rtl838x_irq_dispatch, domain);
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rtl83xx_ictl_base = of_iomap(node, 0);
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if (!rtl83xx_ictl_base)
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return;
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/* Disable all cascaded interrupts */
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rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
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/* Set up interrupt routing */
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rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
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rtl83xx_w32(RTL83XX_IRR1_SETTING, REG(RTL83XX_IRR1));
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rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
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rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
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/* Clear timer interrupt */
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write_c0_compare(0);
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/* Enable all CPU interrupts */
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write_c0_status(read_c0_status() | ST0_IM);
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/* Enable timer0 and uart0 interrupts */
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rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
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}
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static struct of_device_id __initdata of_irq_ids[] = {
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{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
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{ .compatible = "realtek,rt8380-intc", .data = icu_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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of_irq_init(of_irq_ids);
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}
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