mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 14:37:57 +00:00
b5f32064ed
Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
49 lines
1.3 KiB
Diff
49 lines
1.3 KiB
Diff
From 347ca56e86c99021fad059b9a8ef101245b8507e Mon Sep 17 00:00:00 2001
|
|
From: Robert Marko <robimarko@gmail.com>
|
|
Date: Fri, 31 Dec 2021 20:38:06 +0100
|
|
Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes
|
|
|
|
Since there is CPU Freq support as well as thermal sensor support
|
|
now for the IPQ8074, add cooling cells to CPU nodes so that they can
|
|
be used as cooling devices using CPU Freq.
|
|
|
|
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
|
|
1 file changed, 4 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
@@ -41,6 +41,7 @@
|
|
enable-method = "psci";
|
|
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
clock-names = "cpu";
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
CPU1: cpu@1 {
|
|
@@ -51,6 +52,7 @@
|
|
next-level-cache = <&L2_0>;
|
|
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
clock-names = "cpu";
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
CPU2: cpu@2 {
|
|
@@ -61,6 +63,7 @@
|
|
next-level-cache = <&L2_0>;
|
|
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
clock-names = "cpu";
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
CPU3: cpu@3 {
|
|
@@ -71,6 +74,7 @@
|
|
next-level-cache = <&L2_0>;
|
|
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
|
|
clock-names = "cpu";
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
L2_0: l2-cache {
|