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openwrt/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi
Dim Fish 0fd9d00cd6
mediatek: add Airoha AN8855 gigabit switch driver 
New revisions of Xiaomi AX3000T with 1.0.84+ stock firmware contain new hardware.
This commit add support for Airoha AN8855 gigabit switch driver with 6.6 kernel patches

Based on https://patchwork.kernel.org/project/netdevbpf/cover/20241209134459.27110-1-ansuelsmth@gmail.com/

Signed-off-by: Dim Fish <dimfish@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16709
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-01-23 15:27:25 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7981.dtsi"
/ {
aliases {
serial0 = &uart0;
led-boot = &led_status_yellow;
led-failsafe = &led_status_yellow;
led-running = &led_status_blue;
led-upgrade = &led_status_yellow;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0 0x40000000 0 0x10000000>;
};
gpio-keys {
compatible = "gpio-keys";
button-mesh {
label = "mesh";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_9>;
linux,input-type = <EV_SW>;
};
button-reset {
label = "reset";
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds: leds {
compatible = "gpio-leds";
led_status_blue: led-status-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led_status_yellow: led-status-yellow {
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
};
mfd: mfd@1 {
compatible = "airoha,an8855-mfd";
reg = <1>;
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&mfd {
efuse {
compatible = "airoha,an8855-efuse";
#nvmem-cell-cells = <0>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
reg = <0xc 0x4>;
};
shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
reg = <0x10 0x4>;
};
shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
reg = <0x14 0x4>;
};
shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
reg = <0x18 0x4>;
};
shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
reg = <0x1c 0x4>;
};
shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
reg = <0x20 0x4>;
};
shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
reg = <0x24 0x4>;
};
shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
reg = <0x28 0x4>;
};
shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
reg = <0x2c 0x4>;
};
shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
reg = <0x30 0x4>;
};
shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
reg = <0x34 0x4>;
};
shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
reg = <0x38 0x4>;
};
shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
reg = <0x4c 0x4>;
};
shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
reg = <0x50 0x4>;
};
shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
reg = <0x54 0x4>;
};
shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
reg = <0x58 0x4>;
};
};
};
ethernet-switch {
compatible = "airoha,an8855-switch";
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
airoha,ext-surge;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
phy-mode = "internal";
phy-handle = <&internal_phy1>;
};
port@1 {
reg = <1>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&internal_phy2>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&internal_phy3>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&internal_phy4>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
mdio {
compatible = "airoha,an8855-mdio";
#address-cells = <1>;
#size-cells = <0>;
internal_phy1: phy@1 {
reg = <1>;
nvmem-cells = <&shift_sel_port0_tx_a>,
<&shift_sel_port0_tx_b>,
<&shift_sel_port0_tx_c>,
<&shift_sel_port0_tx_d>;
nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
};
internal_phy2: phy@2 {
reg = <2>;
nvmem-cells = <&shift_sel_port1_tx_a>,
<&shift_sel_port1_tx_b>,
<&shift_sel_port1_tx_c>,
<&shift_sel_port1_tx_d>;
nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
};
internal_phy3: phy@3 {
reg = <3>;
nvmem-cells = <&shift_sel_port2_tx_a>,
<&shift_sel_port2_tx_b>,
<&shift_sel_port2_tx_c>,
<&shift_sel_port2_tx_d>;
nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
};
internal_phy4: phy@4 {
reg = <4>;
nvmem-cells = <&shift_sel_port3_tx_a>,
<&shift_sel_port3_tx_b>,
<&shift_sel_port3_tx_c>,
<&shift_sel_port3_tx_d>;
nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions: partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00 0x100000>;
read-only;
};
partition@100000 {
label = "Nvram";
reg = <0x100000 0x40000>;
};
partition@140000 {
label = "Bdata";
reg = <0x140000 0x40000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x200000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom_factory_0: eeprom@0 {
reg = <0x0 0x1000>;
};
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x200000>;
read-only;
};
partition@580000 {
label = "crash";
reg = <0x580000 0x40000>;
read-only;
};
partition@5c0000 {
label = "crash_log";
reg = <0x5c0000 0x40000>;
read-only;
};
partition@7600000 {
label = "KF";
reg = <0x7600000 0x40000>;
read-only;
};
};
};
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
};
&wifi {
status = "okay";
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
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