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https://github.com/openwrt/openwrt.git
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9300eda00f
replace our downstream version of the patches with the ones that were sent upstream. Signed-off-by: John Crispin <john@phrozen.org>
230 lines
6.7 KiB
Diff
230 lines
6.7 KiB
Diff
From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 13:24:07 +0100
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Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT
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optional
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It can be autodetected for many SoCs using the strapping options.
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If the clock is specified in DT, the autodetected value is ignored
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++--------------------------
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1 file changed, 40 insertions(+), 44 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_
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return clk;
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}
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+static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
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+{
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+ struct clk *clk = clks[ATH79_CLK_REF];
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+
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+ if (clk)
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+ rate = clk_get_rate(clk);
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+ else
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+ clk = ath79_set_clk(ATH79_CLK_REF, rate);
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+
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+ return rate;
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+}
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+
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static void __init ar71xx_clocks_init(void __iomem *pll_base)
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{
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unsigned long ref_rate;
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@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo
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u32 freq;
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u32 div;
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- ref_rate = AR71XX_BASE_FREQ;
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+ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
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pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
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@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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- ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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}
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-static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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+static void __init ar724x_clocks_init(void __iomem *pll_base)
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{
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- u32 pll;
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u32 mult, div, ddr_div, ahb_div;
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+ u32 pll;
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+
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+ ath79_setup_ref_clk(AR71XX_BASE_FREQ);
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pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
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@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc
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ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
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}
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-static void __init ar724x_clocks_init(void __iomem *pll_base)
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-{
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- struct clk *ref_clk;
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-
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- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
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-
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- ar724x_clk_init(ref_clk, pll_base);
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-}
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-
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-static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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+static void __init ar933x_clocks_init(void __iomem *pll_base)
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{
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+ unsigned long ref_rate;
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u32 clock_ctrl;
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u32 ref_div;
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u32 ninit_mul;
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@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc
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u32 cpu_div;
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u32 ddr_div;
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u32 ahb_div;
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+ u32 t;
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+
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+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = (40 * 1000 * 1000);
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+ else
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+ ref_rate = (25 * 1000 * 1000);
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+
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+ ath79_setup_ref_clk(ref_rate);
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clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc
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ref_div * out_div * ahb_div);
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}
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-static void __init ar933x_clocks_init(void __iomem *pll_base)
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-{
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- struct clk *ref_clk;
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- unsigned long ref_rate;
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- u32 t;
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-
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- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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- ref_rate = (40 * 1000 * 1000);
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- else
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- ref_rate = (25 * 1000 * 1000);
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-
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- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
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-
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- ar9330_clk_init(ref_clk, ath79_pll_base);
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-}
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-
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static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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u32 frac, u32 out_div)
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{
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@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo
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else
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ref_rate = 25 * 1000 * 1000;
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+ ref_rate = ath79_setup_ref_clk(ref_rate);
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+
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pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
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if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
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@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v
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else
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ref_rate = 25 * 1000 * 1000;
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+ ref_rate = ath79_setup_ref_clk(ref_rate);
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+
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pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v
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else
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ref_rate = 25 * 1000 * 1000;
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+ ref_rate = ath79_setup_ref_clk(ref_rate);
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+
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pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
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@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v
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else
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ref_rate = 25 * 1000 * 1000;
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+ ref_rate = ath79_setup_ref_clk(ref_rate);
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+
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pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
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@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_
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void __iomem *pll_base;
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ref_clk = of_clk_get(np, 0);
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- if (IS_ERR(ref_clk)) {
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- pr_err("%pOF: of_clk_get failed\n", np);
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- goto err;
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- }
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+ if (!IS_ERR(ref_clk))
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+ clks[ATH79_CLK_REF] = ref_clk;
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pll_base = of_iomap(np, 0);
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if (!pll_base) {
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@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_
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}
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if (of_device_is_compatible(np, "qca,ar9130-pll"))
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- ar724x_clk_init(ref_clk, pll_base);
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+ ar724x_clocks_init(pll_base);
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else if (of_device_is_compatible(np, "qca,ar9330-pll"))
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- ar9330_clk_init(ref_clk, pll_base);
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+ ar933x_clocks_init(pll_base);
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else {
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pr_err("%pOF: could not find any appropriate clk_init()\n", np);
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goto err_iounmap;
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@@ -714,9 +713,6 @@ err_iounmap:
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err_clk:
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clk_put(ref_clk);
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-
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-err:
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- return;
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}
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CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
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CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
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