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fce21ae4cc
Right now all brcm2708 patches are extracted from the non-mainline raspberrypi/linux git tree. Many of them are hacks and/or are unneeded in LEDE. Raspberry Pi is getting better and better mainline support so it would be nice to finally start maintaining patches in a cleaner way: 1) Backport patches accepted in upstream tree 2) Start using upstream drivers 3) Pick only these patches that are needed for more complete support Handling above tasks requires grouping patches - ideally using the same prefixes as generic ones. It means we should rename existing patches to use some high prefix. This will allow e.g. use 0xx for backported code. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Stijn Tintel <stijn@linux-ipv6.be>
114 lines
3.9 KiB
Diff
114 lines
3.9 KiB
Diff
From 3b162fdf85d89829d58bbee2d7d79987aceaa595 Mon Sep 17 00:00:00 2001
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From: Boris Brezillon <boris.brezillon@free-electrons.com>
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Date: Fri, 2 Dec 2016 14:48:07 +0100
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Subject: [PATCH] drm/vc4: Fix ->clock_select setting for the VEC encoder
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PV_CONTROL_CLK_SELECT_VEC is actually 2 and not 0. Fix the definition and
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rework the vc4_set_crtc_possible_masks() to cover the full range of the
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PV_CONTROL_CLK_SELECT field.
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Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit ab8df60e3a3b68420d0d4477c5f07c00fbfb078b)
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 38 +++++++++++++++++++++++---------------
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drivers/gpu/drm/vc4/vc4_drv.h | 1 +
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drivers/gpu/drm/vc4/vc4_regs.h | 3 ++-
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3 files changed, 26 insertions(+), 16 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -83,8 +83,7 @@ struct vc4_crtc_data {
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/* Which channel of the HVS this pixelvalve sources from. */
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int hvs_channel;
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- enum vc4_encoder_type encoder0_type;
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- enum vc4_encoder_type encoder1_type;
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+ enum vc4_encoder_type encoder_types[4];
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};
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#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
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@@ -880,20 +879,26 @@ static const struct drm_crtc_helper_func
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static const struct vc4_crtc_data pv0_data = {
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.hvs_channel = 0,
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- .encoder0_type = VC4_ENCODER_TYPE_DSI0,
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- .encoder1_type = VC4_ENCODER_TYPE_DPI,
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+ .encoder_types = {
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+ [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
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+ [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
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+ },
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};
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static const struct vc4_crtc_data pv1_data = {
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.hvs_channel = 2,
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- .encoder0_type = VC4_ENCODER_TYPE_DSI1,
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- .encoder1_type = VC4_ENCODER_TYPE_SMI,
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+ .encoder_types = {
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+ [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
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+ [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
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+ },
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};
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static const struct vc4_crtc_data pv2_data = {
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.hvs_channel = 1,
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- .encoder0_type = VC4_ENCODER_TYPE_VEC,
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- .encoder1_type = VC4_ENCODER_TYPE_HDMI,
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+ .encoder_types = {
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+ [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
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+ [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
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+ },
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};
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static const struct of_device_id vc4_crtc_dt_match[] = {
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@@ -907,17 +912,20 @@ static void vc4_set_crtc_possible_masks(
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struct drm_crtc *crtc)
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{
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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+ const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
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+ const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
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struct drm_encoder *encoder;
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drm_for_each_encoder(encoder, drm) {
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struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
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+ int i;
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- if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
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- vc4_encoder->clock_select = 0;
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- encoder->possible_crtcs |= drm_crtc_mask(crtc);
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- } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
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- vc4_encoder->clock_select = 1;
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- encoder->possible_crtcs |= drm_crtc_mask(crtc);
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+ for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
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+ if (vc4_encoder->type == encoder_types[i]) {
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+ vc4_encoder->clock_select = i;
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+ encoder->possible_crtcs |= drm_crtc_mask(crtc);
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+ break;
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+ }
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}
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}
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}
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -197,6 +197,7 @@ to_vc4_plane(struct drm_plane *plane)
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}
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enum vc4_encoder_type {
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+ VC4_ENCODER_TYPE_NONE,
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VC4_ENCODER_TYPE_HDMI,
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VC4_ENCODER_TYPE_VEC,
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VC4_ENCODER_TYPE_DSI0,
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -177,8 +177,9 @@
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# define PV_CONTROL_WAIT_HSTART BIT(12)
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# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
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# define PV_CONTROL_PIXEL_REP_SHIFT 4
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-# define PV_CONTROL_CLK_SELECT_DSI_VEC 0
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+# define PV_CONTROL_CLK_SELECT_DSI 0
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# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
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+# define PV_CONTROL_CLK_SELECT_VEC 2
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# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
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# define PV_CONTROL_CLK_SELECT_SHIFT 2
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# define PV_CONTROL_FIFO_CLR BIT(1)
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