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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
47 lines
1.7 KiB
Diff
47 lines
1.7 KiB
Diff
From b5f843fe7ece2b75a783fa785d6c7c6647a7a46d Mon Sep 17 00:00:00 2001
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From: Michiiel <94533767+Michiiel@users.noreply.github.com>
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Date: Thu, 30 May 2024 15:43:21 +0200
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Subject: [PATCH 1109/1135] =?UTF-8?q?fix=20Hsync=20and=20Vsync=20polarity?=
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=?UTF-8?q?=20can't=20change=20from=20negatieve=20to=20positief=20?=
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=?UTF-8?q?=E2=80=A6=20(#6193)?=
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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vc4/hdmi: Fix Hsync and Vsync polarity changes
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Polarity bits were only ever set and never cleared.
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Make sure they can also be cleared.
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Signed-off-by: Michiel Vanbiervliet <michiel.vanbiervliet@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 17 +++++++++--------
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1 file changed, 9 insertions(+), 8 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -1883,14 +1883,15 @@ static void vc4_hdmi_encoder_post_crtc_e
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spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
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HDMI_WRITE(HDMI_VID_CTL,
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- HDMI_READ(HDMI_VID_CTL) |
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- VC4_HD_VID_CTL_ENABLE |
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- VC4_HD_VID_CTL_CLRRGB |
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- VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
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- VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
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- VC4_HD_VID_CTL_BLANK_INSERT_EN |
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- (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
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- (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
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+ (HDMI_READ(HDMI_VID_CTL) &~
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+ (VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) |
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+ VC4_HD_VID_CTL_ENABLE |
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+ VC4_HD_VID_CTL_CLRRGB |
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+ VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
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+ VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
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+ VC4_HD_VID_CTL_BLANK_INSERT_EN |
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+ (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
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+ (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
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HDMI_WRITE(HDMI_VID_CTL,
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HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
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