mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
168 lines
4.8 KiB
Diff
168 lines
4.8 KiB
Diff
From a8124c63760bac96853d2aee2c95a2f29c870f69 Mon Sep 17 00:00:00 2001
|
|
From: Maxime Ripard <maxime@cerno.tech>
|
|
Date: Fri, 17 Feb 2023 15:14:55 +0100
|
|
Subject: [PATCH 0591/1085] drm/vc4: hvs: Create cob_init function
|
|
|
|
Just like the HVS itself, the COB parameters will be fairly different in
|
|
the BCM2712.
|
|
|
|
Let's move the COB parameters computation and its initialisation to a
|
|
separate function that will be easier to extend in the future.
|
|
|
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_hvs.c | 128 ++++++++++++++++++++--------------
|
|
1 file changed, 74 insertions(+), 54 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
|
|
@@ -1369,6 +1369,77 @@ static int vc4_hvs_hw_init(struct vc4_hv
|
|
return 0;
|
|
}
|
|
|
|
+static int vc4_hvs_cob_init(struct vc4_hvs *hvs)
|
|
+{
|
|
+ struct vc4_dev *vc4 = hvs->vc4;
|
|
+ u32 reg, top;
|
|
+
|
|
+ /*
|
|
+ * Recompute Composite Output Buffer (COB) allocations for the
|
|
+ * displays
|
|
+ */
|
|
+ switch (vc4->gen) {
|
|
+ case VC4_GEN_4:
|
|
+ /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
|
|
+ * The bottom 2048 pixels are full 32bpp RGBA (intended for the
|
|
+ * TXP composing RGBA to memory), whilst the remainder are only
|
|
+ * 24bpp RGB.
|
|
+ *
|
|
+ * Assign 3 lines to channels 1 & 2, and just over 4 lines to
|
|
+ * channel 0.
|
|
+ */
|
|
+ #define VC4_COB_SIZE 20736
|
|
+ #define VC4_COB_LINE_WIDTH 2048
|
|
+ #define VC4_COB_NUM_LINES 3
|
|
+ reg = 0;
|
|
+ top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
|
|
+ reg |= (top - 1) << 16;
|
|
+ HVS_WRITE(SCALER_DISPBASE2, reg);
|
|
+ reg = top;
|
|
+ top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
|
|
+ reg |= (top - 1) << 16;
|
|
+ HVS_WRITE(SCALER_DISPBASE1, reg);
|
|
+ reg = top;
|
|
+ top = VC4_COB_SIZE;
|
|
+ reg |= (top - 1) << 16;
|
|
+ HVS_WRITE(SCALER_DISPBASE0, reg);
|
|
+ break;
|
|
+
|
|
+ case VC4_GEN_5:
|
|
+ /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
|
|
+ * The bottom 4096 pixels are full RGBA (intended for the TXP
|
|
+ * composing RGBA to memory), whilst the remainder are only
|
|
+ * RGB. Addressing is always pixel wide.
|
|
+ *
|
|
+ * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
|
|
+ * lines. to channel 0.
|
|
+ */
|
|
+ #define VC5_COB_SIZE 44416
|
|
+ #define VC5_COB_LINE_WIDTH 4096
|
|
+ #define VC5_COB_NUM_LINES 3
|
|
+ reg = 0;
|
|
+ top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
|
|
+ reg |= top << 16;
|
|
+ HVS_WRITE(SCALER_DISPBASE2, reg);
|
|
+ top += 16;
|
|
+ reg = top;
|
|
+ top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
|
|
+ reg |= top << 16;
|
|
+ HVS_WRITE(SCALER_DISPBASE1, reg);
|
|
+ top += 16;
|
|
+ reg = top;
|
|
+ top = VC5_COB_SIZE;
|
|
+ reg |= top << 16;
|
|
+ HVS_WRITE(SCALER_DISPBASE0, reg);
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
@@ -1376,7 +1447,6 @@ static int vc4_hvs_bind(struct device *d
|
|
struct vc4_dev *vc4 = to_vc4_dev(drm);
|
|
struct vc4_hvs *hvs = NULL;
|
|
int ret;
|
|
- u32 reg, top;
|
|
|
|
hvs = __vc4_hvs_alloc(vc4, NULL);
|
|
if (IS_ERR(hvs))
|
|
@@ -1446,59 +1516,9 @@ static int vc4_hvs_bind(struct device *d
|
|
if (ret)
|
|
return ret;
|
|
|
|
- /* Recompute Composite Output Buffer (COB) allocations for the displays
|
|
- */
|
|
- if (vc4->gen == VC4_GEN_4) {
|
|
- /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
|
|
- * The bottom 2048 pixels are full 32bpp RGBA (intended for the
|
|
- * TXP composing RGBA to memory), whilst the remainder are only
|
|
- * 24bpp RGB.
|
|
- *
|
|
- * Assign 3 lines to channels 1 & 2, and just over 4 lines to
|
|
- * channel 0.
|
|
- */
|
|
- #define VC4_COB_SIZE 20736
|
|
- #define VC4_COB_LINE_WIDTH 2048
|
|
- #define VC4_COB_NUM_LINES 3
|
|
- reg = 0;
|
|
- top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
|
|
- reg |= (top - 1) << 16;
|
|
- HVS_WRITE(SCALER_DISPBASE2, reg);
|
|
- reg = top;
|
|
- top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
|
|
- reg |= (top - 1) << 16;
|
|
- HVS_WRITE(SCALER_DISPBASE1, reg);
|
|
- reg = top;
|
|
- top = VC4_COB_SIZE;
|
|
- reg |= (top - 1) << 16;
|
|
- HVS_WRITE(SCALER_DISPBASE0, reg);
|
|
- } else {
|
|
- /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
|
|
- * The bottom 4096 pixels are full RGBA (intended for the TXP
|
|
- * composing RGBA to memory), whilst the remainder are only
|
|
- * RGB. Addressing is always pixel wide.
|
|
- *
|
|
- * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
|
|
- * lines. to channel 0.
|
|
- */
|
|
- #define VC5_COB_SIZE 44416
|
|
- #define VC5_COB_LINE_WIDTH 4096
|
|
- #define VC5_COB_NUM_LINES 3
|
|
- reg = 0;
|
|
- top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
|
|
- reg |= top << 16;
|
|
- HVS_WRITE(SCALER_DISPBASE2, reg);
|
|
- top += 16;
|
|
- reg = top;
|
|
- top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
|
|
- reg |= top << 16;
|
|
- HVS_WRITE(SCALER_DISPBASE1, reg);
|
|
- top += 16;
|
|
- reg = top;
|
|
- top = VC5_COB_SIZE;
|
|
- reg |= top << 16;
|
|
- HVS_WRITE(SCALER_DISPBASE0, reg);
|
|
- }
|
|
+ ret = vc4_hvs_cob_init(hvs);
|
|
+ if (ret)
|
|
+ return ret;
|
|
|
|
ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
|
|
vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
|