mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 14:37:57 +00:00
41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From 3f55310c00b8c478da1458704027036c1a414973 Mon Sep 17 00:00:00 2001
|
|
From: Claudiu Beznea <claudiu.beznea@microchip.com>
|
|
Date: Thu, 15 Apr 2021 13:50:03 +0300
|
|
Subject: [PATCH 212/247] ARM: at91: pm: add sama7g5 ddr controller
|
|
|
|
Add SAMA7G5 DDR controller to the list of DDR controller compatibles.
|
|
At the moment there is no standby support. Adapt the code for this.
|
|
|
|
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
|
|
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
|
|
Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com
|
|
---
|
|
arch/arm/mach-at91/pm.c | 9 ++++++---
|
|
1 file changed, 6 insertions(+), 3 deletions(-)
|
|
|
|
--- a/arch/arm/mach-at91/pm.c
|
|
+++ b/arch/arm/mach-at91/pm.c
|
|
@@ -548,6 +548,7 @@ static const struct of_device_id ramc_id
|
|
{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
|
|
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
|
|
{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
|
|
+ { .compatible = "microchip,sama7g5-uddrc", },
|
|
{ /*sentinel*/ }
|
|
};
|
|
|
|
@@ -569,9 +570,11 @@ static __init int at91_dt_ramc(void)
|
|
}
|
|
|
|
ramc = of_id->data;
|
|
- if (!standby)
|
|
- standby = ramc->idle;
|
|
- soc_pm.data.memctrl = ramc->memctrl;
|
|
+ if (ramc) {
|
|
+ if (!standby)
|
|
+ standby = ramc->idle;
|
|
+ soc_pm.data.memctrl = ramc->memctrl;
|
|
+ }
|
|
|
|
idx++;
|
|
}
|