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86 lines
3.1 KiB
Diff
86 lines
3.1 KiB
Diff
From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Wed, 9 Dec 2020 15:03:33 +0200
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Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate
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SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or
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by the external clock provided by the PHY. The internal IP logic divides
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properly this clock depending on the link speed. The patch adds a new
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capability so that macb_set_tx_clock() to not be called for IPs having
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this capability (the clock rate, in case of generic clock, is set at the
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boot time via device tree and the driver only enables it).
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/cadence/macb.h | 1 +
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drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++---------
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2 files changed, 10 insertions(+), 9 deletions(-)
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--- a/drivers/net/ethernet/cadence/macb.h
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+++ b/drivers/net/ethernet/cadence/macb.h
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@@ -658,6 +658,7 @@
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#define MACB_CAPS_GEM_HAS_PTP 0x00000040
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#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
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#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
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+#define MACB_CAPS_CLK_HW_CHG 0x04000000
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#define MACB_CAPS_MACB_IS_EMAC 0x08000000
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#define MACB_CAPS_FIFO_MODE 0x10000000
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#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
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--- a/drivers/net/ethernet/cadence/macb_main.c
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+++ b/drivers/net/ethernet/cadence/macb_main.c
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@@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac
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/**
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* macb_set_tx_clk() - Set a clock to a new frequency
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- * @clk: Pointer to the clock to change
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+ * @bp: pointer to struct macb
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* @speed: New frequency in Hz
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- * @dev: Pointer to the struct net_device
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*/
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-static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
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+static void macb_set_tx_clk(struct macb *bp, int speed)
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{
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long ferr, rate, rate_rounded;
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- if (!clk)
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+ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
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return;
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switch (speed) {
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@@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk *
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return;
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}
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- rate_rounded = clk_round_rate(clk, rate);
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+ rate_rounded = clk_round_rate(bp->tx_clk, rate);
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if (rate_rounded < 0)
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return;
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@@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk *
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ferr = abs(rate_rounded - rate);
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ferr = DIV_ROUND_UP(ferr, rate / 100000);
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if (ferr > 5)
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- netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
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+ netdev_warn(bp->dev,
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+ "unable to generate target frequency: %ld Hz\n",
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rate);
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- if (clk_set_rate(clk, rate_rounded))
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- netdev_err(dev, "adjusting tx_clk failed.\n");
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+ if (clk_set_rate(bp->tx_clk, rate_rounded))
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+ netdev_err(bp->dev, "adjusting tx_clk failed.\n");
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}
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static void macb_validate(struct phylink_config *config,
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@@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl
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if (rx_pause)
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ctrl |= MACB_BIT(PAE);
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- macb_set_tx_clk(bp->tx_clk, speed, ndev);
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+ macb_set_tx_clk(bp, speed);
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/* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
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* cleared the pipeline and control registers.
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