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https://github.com/openwrt/openwrt.git
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81bd10e4a2
Remove DTS_LEGACY put for claiming pin groups for the ethernet node from
the ethernet node. It's not an old kernel trait. These bindings need to be
there on the newer kernels as well.
Fixes: a3764ee29d ("ramips: add linux 5.15 support for mt7621")
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
693 lines
13 KiB
Plaintext
693 lines
13 KiB
Plaintext
/dts-v1/;
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/clock/mt7621-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7621-soc";
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aliases {
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serial0 = &uartlite;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips1004Kc";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "mips,mips1004Kc";
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reg = <1>;
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};
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};
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cpuintc: cpuintc {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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#ifdef DTS_LEGACY
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pll: pll {
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compatible = "mediatek,mt7621-pll", "syscon";
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#clock-cells = <1>;
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clock-output-names = "cpu", "bus";
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};
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#endif
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sysclock: sysclock {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* FIXME: there should be way to detect this */
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clock-frequency = <50000000>;
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};
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palmbus: palmbus@1e000000 {
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compatible = "palmbus";
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reg = <0x1e000000 0x100000>;
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ranges = <0x0 0x1e000000 0x0fffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: syscon@0 {
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#ifdef DTS_LEGACY
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compatible = "mtk,mt7621-sysc", "syscon";
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#else
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compatible = "mediatek,mt7621-sysc", "syscon";
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#clock-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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"250m", "270m";
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#endif
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reg = <0x0 0x100>;
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};
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wdt: wdt@100 {
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compatible = "mediatek,mt7621-wdt";
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reg = <0x100 0x100>;
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};
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gpio: gpio@600 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "mediatek,mt7621-gpio";
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 95>;
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interrupt-controller;
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reg = <0x600 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c: i2c@900 {
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compatible = "mediatek,mt7621-i2c";
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reg = <0x900 0x100>;
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clocks = <&sysclock>;
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resets = <&rstctrl 16>;
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reset-names = "i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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};
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i2s: i2s@a00 {
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compatible = "mediatek,mt7621-i2s";
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reg = <0xa00 0x100>;
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clocks = <&sysclock>;
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resets = <&rstctrl 17>;
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reset-names = "i2s";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
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txdma-req = <2>;
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rxdma-req = <3>;
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dmas = <&gdma 4>,
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<&gdma 6>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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systick: systick@500 {
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compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
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reg = <0x500 0x10>;
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resets = <&rstctrl 28>;
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reset-names = "intc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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memc: syscon@5000 {
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#ifdef DTS_LEGACY
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compatible = "mtk,mt7621-memc", "syscon";
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#else
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compatible = "mediatek,mt7621-memc", "syscon";
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#endif
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reg = <0x5000 0x1000>;
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};
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uartlite: uartlite@c00 {
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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clock-frequency = <50000000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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};
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uartlite2: uartlite2@d00 {
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compatible = "ns16550a";
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reg = <0xd00 0x100>;
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clock-frequency = <50000000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "disabled";
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};
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uartlite3: uartlite3@e00 {
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compatible = "ns16550a";
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reg = <0xe00 0x100>;
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clock-frequency = <50000000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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status = "disabled";
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};
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spi0: spi@b00 {
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status = "disabled";
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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#ifdef DTS_LEGACY
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clocks = <&pll MT7621_CLK_BUS>;
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#else
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clocks = <&sysc MT7621_CLK_BUS>;
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#endif
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resets = <&rstctrl 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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};
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gdma: gdma@2800 {
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compatible = "ralink,rt3883-gdma";
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reg = <0x2800 0x800>;
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resets = <&rstctrl 14>;
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reset-names = "dma";
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interrupt-parent = <&gic>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <16>;
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#dma-requests = <16>;
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status = "disabled";
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};
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hsdma: hsdma@7000 {
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compatible = "mediatek,mt7621-hsdma";
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reg = <0x7000 0x1000>;
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resets = <&rstctrl 5>;
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reset-names = "hsdma";
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interrupt-parent = <&gic>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <1>;
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#dma-requests = <1>;
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status = "disabled";
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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};
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i2c_pins: i2c_pins {
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i2c_pins {
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groups = "i2c";
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function = "i2c";
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};
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};
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spi_pins: spi_pins {
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spi_pins {
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groups = "spi";
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function = "spi";
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};
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};
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uart1_pins: uart1 {
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uart1 {
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groups = "uart1";
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function = "uart1";
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};
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};
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uart2_pins: uart2 {
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uart2 {
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groups = "uart2";
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function = "uart2";
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};
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};
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uart3_pins: uart3 {
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uart3 {
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groups = "uart3";
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function = "uart3";
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};
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};
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rgmii1_pins: rgmii1 {
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rgmii1 {
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groups = "rgmii1";
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function = "rgmii1";
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};
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};
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rgmii2_pins: rgmii2 {
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rgmii2 {
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groups = "rgmii2";
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function = "rgmii2";
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};
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};
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mdio_pins: mdio {
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mdio {
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groups = "mdio";
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function = "mdio";
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};
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};
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pcie_pins: pcie {
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pcie {
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groups = "pcie";
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function = "gpio";
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};
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};
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nand_pins: nand {
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spi-nand {
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groups = "spi";
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function = "nand1";
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};
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sdhci-nand {
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groups = "sdhci";
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function = "nand2";
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};
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};
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sdhci_pins: sdhci {
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sdhci {
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groups = "sdhci";
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function = "sdhci";
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};
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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clkctrl: clkctrl {
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compatible = "ralink,rt2880-clock";
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#clock-cells = <1>;
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};
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sdhci: sdhci@1e130000 {
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status = "disabled";
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compatible = "ralink,mt7620-sdhci";
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reg = <0x1e130000 0x4000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdhci_pins>;
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};
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xhci: xhci@1e1c0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mediatek,mt8173-xhci";
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reg = <0x1e1c0000 0x1000
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0x1e1d0700 0x0100>;
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reg-names = "mac", "ippc";
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clocks = <&sysclock>;
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clock-names = "sys_ck";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
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/*
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* Port 1 of both hubs is one usb slot and referenced here.
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* The binding doesn't allow to address individual hubs.
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* hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
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*/
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xhci_ehci_port1: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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/*
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* Only the second usb hub has a second port. That port serves
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* ehci and ohci.
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*/
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ehci_port2: port@2 {
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reg = <2>;
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#trigger-source-cells = <0>;
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};
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};
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gic: interrupt-controller@1fbc0000 {
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compatible = "mti,gic";
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reg = <0x1fbc0000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mti,reserved-cpu-vectors = <7>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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#ifdef DTS_LEGACY
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clocks = <&pll MT7621_CLK_CPU>;
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#else
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clocks = <&sysc MT7621_CLK_CPU>;
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#endif
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};
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};
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nficlock: nficlock {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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};
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cpc: cpc@1fbf0000 {
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compatible = "mti,mips-cpc";
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reg = <0x1fbf0000 0x8000>;
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};
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mc: mc@1fbf8000 {
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compatible = "mti,mips-cdmm";
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reg = <0x1fbf8000 0x8000>;
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};
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nand: nand@1e003000 {
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status = "disabled";
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compatible = "mediatek,mt7621-nfc";
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reg = <0x1e003000 0x800
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0x1e003800 0x800>;
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reg-names = "nfi", "ecc";
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clocks = <&nficlock>;
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clock-names = "nfi_clk";
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};
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ethernet: ethernet@1e100000 {
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compatible = "mediatek,mt7621-eth";
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reg = <0x1e100000 0x10000>;
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#ifdef DTS_LEGACY
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clocks = <&sysclock>;
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clock-names = "ethif";
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#else
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clocks = <&sysc MT7621_CLK_FE>,
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<&sysc MT7621_CLK_ETH>;
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clock-names = "fe", "ethif";
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#endif
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rstctrl 6>, <&rstctrl 23>;
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reset-names = "fe", "eth";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
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mediatek,ethsys = <&sysc>;
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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status = "disabled";
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phy-mode = "rgmii-rxid";
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0: switch@1f {
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compatible = "mediatek,mt7621";
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reg = <0x1f>;
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mediatek,mcm;
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resets = <&rstctrl 2>;
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reset-names = "mcm";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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status = "disabled";
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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status = "disabled";
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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status = "disabled";
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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status = "disabled";
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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status = "disabled";
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reg = <4>;
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label = "lan4";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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pcie: pcie@1e140000 {
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compatible = "mediatek,mt7621-pci";
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reg = <0x1e140000 0x100>, /* host-pci bridge registers */
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<0x1e142000 0x100>, /* pcie port 0 RC control registers */
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<0x1e143000 0x100>, /* pcie port 1 RC control registers */
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<0x1e144000 0x100>; /* pcie port 2 RC control registers */
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#address-cells = <3>;
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#size-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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device_type = "pci";
|
|
|
|
#ifdef DTS_LEGACY
|
|
ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
|
|
<0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
|
|
#else
|
|
ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
|
|
<0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
|
|
#endif
|
|
|
|
status = "disabled";
|
|
|
|
#ifdef DTS_LEGACY
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
|
resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
|
|
reset-names = "pcie0", "pcie1", "pcie2";
|
|
clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
|
|
clock-names = "pcie0", "pcie1", "pcie2";
|
|
phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
|
|
phy-names = "pcie-phy0", "pcie-phy2";
|
|
#else
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0xF800 0 0 0>;
|
|
interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
#endif
|
|
|
|
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
|
|
|
|
pcie0: pcie@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
ranges;
|
|
#ifndef DTS_LEGACY
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&rstctrl 24>;
|
|
clocks = <&sysc MT7621_CLK_PCIE0>;
|
|
phys = <&pcie0_phy 1>;
|
|
phy-names = "pcie-phy0";
|
|
#endif
|
|
};
|
|
|
|
pcie1: pcie@1,0 {
|
|
reg = <0x0800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
ranges;
|
|
#ifndef DTS_LEGACY
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&rstctrl 25>;
|
|
clocks = <&sysc MT7621_CLK_PCIE1>;
|
|
phys = <&pcie0_phy 1>;
|
|
phy-names = "pcie-phy1";
|
|
#endif
|
|
};
|
|
|
|
pcie2: pcie@2,0 {
|
|
reg = <0x1000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
ranges;
|
|
#ifndef DTS_LEGACY
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&rstctrl 26>;
|
|
clocks = <&sysc MT7621_CLK_PCIE2>;
|
|
phys = <&pcie2_phy 0>;
|
|
phy-names = "pcie-phy2";
|
|
#endif
|
|
};
|
|
};
|
|
|
|
pcie0_phy: pcie-phy@1e149000 {
|
|
compatible = "mediatek,mt7621-pci-phy";
|
|
reg = <0x1e149000 0x0700>;
|
|
#ifndef DTS_LEGACY
|
|
clocks = <&sysc MT7621_CLK_XTAL>;
|
|
#endif
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
pcie2_phy: pcie-phy@1e14a000 {
|
|
compatible = "mediatek,mt7621-pci-phy";
|
|
reg = <0x1e14a000 0x0700>;
|
|
#ifndef DTS_LEGACY
|
|
clocks = <&sysc MT7621_CLK_XTAL>;
|
|
#endif
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|