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166 lines
4.5 KiB
Diff
166 lines
4.5 KiB
Diff
From 78e92290c8c9511d0d540dfd0450e64169f08c20 Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Mon, 5 Feb 2018 22:44:44 +0800
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Subject: [PATCH 213/224] arm64: dts: mt7622: add PMIC MT6380 related nodes
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Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
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regulator nodes in an alone file to allow similar boards using MT6380
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able to resue the configuration.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Cc: Mark Brown <broonie@kernel.org>
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Cc: Matthias Brugger <matthias.bgg@gmail.com>
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Cc: Philippe Ombredanne <pombredanne@nexb.com>
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Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
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---
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arch/arm64/boot/dts/mediatek/mt6380.dtsi | 86 ++++++++++++++++++++++++++++
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
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3 files changed, 106 insertions(+)
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create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
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diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
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new file mode 100644
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index 000000000000..53b335d2de5f
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
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@@ -0,0 +1,86 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * dts file for MediaTek MT6380 regulator
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+ *
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+ * Copyright (c) 2018 MediaTek Inc.
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+ * Author: Chenglin Xu <chenglin.xu@mediatek.com>
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+ * Sean Wang <sean.wang@mediatek.com>
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+ */
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+
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+&pwrap {
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+ regulators {
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+ compatible = "mediatek,mt6380-regulator";
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+
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+ mt6380_vcpu_reg: buck-vcore1 {
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+ regulator-name = "vcore1";
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+ regulator-min-microvolt = < 600000>;
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+ regulator-max-microvolt = <1393750>;
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+ regulator-ramp-delay = <6250>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6380_vcore_reg: buck-vcore {
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+ regulator-name = "vcore";
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+ regulator-min-microvolt = <600000>;
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+ regulator-max-microvolt = <1393750>;
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+ regulator-ramp-delay = <6250>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6380_vrf_reg: buck-vrf {
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+ regulator-name = "vrf";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <1575000>;
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+ regulator-ramp-delay = <0>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6380_vm_reg: ldo-vm {
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+ regulator-name = "vm";
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+ regulator-min-microvolt = <1050000>;
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+ regulator-max-microvolt = <1400000>;
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+ regulator-ramp-delay = <0>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6380_va_reg: ldo-va {
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+ regulator-name = "va";
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+ regulator-min-microvolt = <2200000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-ramp-delay = <0>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6380_vphy_reg: ldo-vphy {
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+ regulator-name = "vphy";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-ramp-delay = <0>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6380_vddr_reg: ldo-vddr {
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+ regulator-name = "vddr";
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+ regulator-min-microvolt = <1240000>;
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+ regulator-max-microvolt = <1840000>;
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+ regulator-ramp-delay = <0>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6380_vt_reg: ldo-vt {
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+ regulator-name = "vt";
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+ regulator-min-microvolt = <2200000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-ramp-delay = <0>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+ };
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+};
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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index fc8ef78a0a34..42bd3a4c9a93 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -10,6 +10,7 @@
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#include <dt-bindings/input/input.h>
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#include "mt7622.dtsi"
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+#include "mt6380.dtsi"
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/ {
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model = "MediaTek MT7622 RFB1 board";
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@@ -222,6 +223,13 @@
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};
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};
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+&pwrap {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pmic_bus_pins>;
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+
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+ status = "okay";
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+};
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+
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&uart0 {
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status = "okay";
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};
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diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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index 8211bf72ccaa..c387c4cb7d3e 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -102,6 +102,18 @@
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#reset-cells = <1>;
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};
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+ pwrap: pwrap@10001000 {
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+ compatible = "mediatek,mt7622-pwrap";
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+ reg = <0 0x10001000 0 0x250>;
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+ reg-names = "pwrap";
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+ clocks = <&infracfg CLK_INFRA_PMIC_PD>,<&pwrap_clk>;
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+ clock-names = "spi","wrap";
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+ resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
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+ reset-names = "pwrap";
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+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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pericfg: pericfg@10002000 {
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compatible = "mediatek,mt7622-pericfg",
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"syscon";
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--
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2.11.0
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