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ac5297340e
Refreshed all patches. Altered patches: - 210-dwc2_defaults.patch - 708-mc-bus-support-layerscape.patch Fixes: - CVE-2020-25656 Compile-tested on: ar71xx, cns3xxx, imx6, x86_64 Runtime-tested on: ar71xx, cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
116 lines
3.7 KiB
Diff
116 lines
3.7 KiB
Diff
From a3927566a6d90268423ae58aad12a71b9bf39dd9 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Mon, 6 Mar 2017 09:06:18 +0000
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Subject: [PATCH 028/454] clk-bcm2835: Read max core clock from firmware
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The VPU is responsible for managing the core clock, usually under
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direction from the bcm2835-cpufreq driver but not via the clk-bcm2835
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driver. Since the core frequency can change without warning, it is
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safer to report the maximum clock rate to users of the core clock -
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I2C, SPI and the mini UART - to err on the safe side when calculating
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clock divisors.
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If the DT node for the clock driver includes a reference to the
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firmware node, use the firmware API to query the maximum core clock
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instead of reading the divider registers.
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Prior to this patch, a "100KHz" I2C bus was sometimes clocked at about
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160KHz. In particular, switching to the 4.9 kernel was likely to break
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SenseHAT usage on a Pi3.
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/clk/bcm/clk-bcm2835.c | 39 ++++++++++++++++++++++++++++++++++-
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1 file changed, 38 insertions(+), 1 deletion(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -45,6 +45,7 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/bcm2835.h>
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+#include <soc/bcm2835/raspberrypi-firmware.h>
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#define CM_PASSWORD 0x5a000000
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@@ -299,6 +300,8 @@
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#define LOCK_TIMEOUT_NS 100000000
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#define BCM2835_MAX_FB_RATE 1750000000u
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+#define VCMSG_ID_CORE_CLOCK 4
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+
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/*
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* Names of clocks used within the driver that need to be replaced
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* with an external parent's name. This array is in the order that
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@@ -317,6 +320,7 @@ static const char *const cprman_parent_n
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struct bcm2835_cprman {
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struct device *dev;
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void __iomem *regs;
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+ struct rpi_firmware *fw;
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spinlock_t regs_lock; /* spinlock for all clocks */
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/*
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@@ -1032,6 +1036,30 @@ static unsigned long bcm2835_clock_get_r
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return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
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}
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+static unsigned long bcm2835_clock_get_rate_vpu(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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+ struct bcm2835_cprman *cprman = clock->cprman;
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+
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+ if (cprman->fw) {
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+ struct {
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+ u32 id;
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+ u32 val;
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+ } packet;
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+
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+ packet.id = VCMSG_ID_CORE_CLOCK;
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+ packet.val = 0;
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+
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+ if (!rpi_firmware_property(cprman->fw,
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+ RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
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+ &packet, sizeof(packet)))
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+ return packet.val;
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+ }
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+
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+ return bcm2835_clock_get_rate(hw, parent_rate);
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+}
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+
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static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
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{
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struct bcm2835_cprman *cprman = clock->cprman;
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@@ -1321,7 +1349,7 @@ static int bcm2835_vpu_clock_is_on(struc
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*/
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static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
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.is_prepared = bcm2835_vpu_clock_is_on,
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- .recalc_rate = bcm2835_clock_get_rate,
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+ .recalc_rate = bcm2835_clock_get_rate_vpu,
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.set_rate = bcm2835_clock_set_rate,
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.determine_rate = bcm2835_clock_determine_rate,
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.set_parent = bcm2835_clock_set_parent,
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@@ -2203,6 +2231,7 @@ static int bcm2835_clk_probe(struct plat
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struct resource *res;
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const struct bcm2835_clk_desc *desc;
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const size_t asize = ARRAY_SIZE(clk_desc_array);
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+ struct device_node *fw_node;
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size_t i;
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u32 clk_id;
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int ret;
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@@ -2220,6 +2249,14 @@ static int bcm2835_clk_probe(struct plat
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if (IS_ERR(cprman->regs))
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return PTR_ERR(cprman->regs);
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+ fw_node = of_parse_phandle(dev->of_node, "firmware", 0);
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+ if (fw_node) {
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+ struct rpi_firmware *fw = rpi_firmware_get(NULL);
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+ if (!fw)
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+ return -EPROBE_DEFER;
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+ cprman->fw = fw;
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+ }
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+
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memset(bcm2835_clk_claimed, 0, sizeof(bcm2835_clk_claimed));
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for (i = 0;
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!of_property_read_u32_index(pdev->dev.of_node, "claim-clocks",
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