mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
61 lines
1.9 KiB
Diff
61 lines
1.9 KiB
Diff
---
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drivers/usb/host/ohci-ssb.c | 39 ++++++++++++++++++++++++++++++++++++---
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1 file changed, 36 insertions(+), 3 deletions(-)
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--- a/drivers/usb/host/ohci-ssb.c
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+++ b/drivers/usb/host/ohci-ssb.c
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@@ -106,10 +106,42 @@ static int ssb_ohci_attach(struct ssb_de
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int err = -ENOMEM;
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u32 tmp, flags = 0;
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- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
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+ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
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+ /* Put the device into host-mode. */
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flags |= SSB_OHCI_TMSLOW_HOSTMODE;
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-
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- ssb_device_enable(dev, flags);
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+ ssb_device_enable(dev, flags);
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+ } else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
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+ /*
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+ * USB 2.0 special considerations:
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+ *
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+ * 1. Since the core supports both OHCI and EHCI functions, it must
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+ * only be reset once.
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+ *
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+ * 2. In addition to the standard SSB reset sequence, the Host Control
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+ * Register must be programmed to bring the USB core and various
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+ * phy components out of reset.
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+ */
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+ ssb_device_enable(dev, 0);
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+ ssb_write32(dev, 0x200, 0x7ff);
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+ udelay(1);
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+ if (dev->id.revision == 1) { // bug in rev 1
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+
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+ /* Change Flush control reg */
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+ tmp = ssb_read32(dev, 0x400);
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+ tmp &= ~8;
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+ ssb_write32(dev, 0x400, tmp);
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+ tmp = ssb_read32(dev, 0x400);
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+ printk("USB20H fcr: 0x%0x\n", tmp);
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+
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+ /* Change Shim control reg */
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+ tmp = ssb_read32(dev, 0x304);
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+ tmp &= ~0x100;
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+ ssb_write32(dev, 0x304, tmp);
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+ tmp = ssb_read32(dev, 0x304);
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+ printk("USB20H shim: 0x%0x\n", tmp);
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+ }
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+ } else
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+ ssb_device_enable(dev, 0);
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hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
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dev_name(dev->dev));
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@@ -200,6 +232,7 @@ static int ssb_ohci_resume(struct ssb_de
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static const struct ssb_device_id ssb_ohci_table[] = {
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SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
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SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
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+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
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SSB_DEVTABLE_END
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};
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MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
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