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e9d92bf1e1
Refreshed all patches. Removed upstreamed: - 203-MIPS-ath79-fix-restart.patch - 0013-MIPS-ath79-fix-system-restart.patch - 180-earlycon-initialize-port-uartclk-based-on-clock-frequency-property.patch - 181-earlycon-remove-hardcoded-port-uartclk-initialization-in-of_setup_earlycon. patch - 700-1-6-e1000e-Remove-Other-from-EIAC.patch - 700-2-6-Partial-revert-e1000e-Avoid-receiver-overrun-interrupt-bursts.patch - 700-3-6-e1000e-Fix-queue-interrupt-re-raising-in-Other-interrupt.patch - 700-4-6-e1000e-Avoid-missed-interrupts-following-ICR-read.patch Compile-tested on: cns3xxx, imx6 Runtime-tested on: cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
104 lines
4.3 KiB
Diff
104 lines
4.3 KiB
Diff
From: Christian Lamparter <chunkeey@gmail.com>
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Date: Thu, 12 Apr 2018 21:01:38 +0200
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Subject: [PATCH] pinctrl: msm: fix gpio-hog related boot issues
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Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
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Setting up any gpio-hog in the device-tree for his device would
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"kill the bootup completely":
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| [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
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| [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe
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| [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517
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| [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register
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| [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip
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| [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
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| [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri
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This was also verified on a RT-AC58U (IPQ4018) which would
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no longer boot, if a gpio-hog was specified. (Tried forcing
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the USB LED PIN (GPIO0) to high.).
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The problem is that Pinctrl+GPIO registration is currently
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peformed in the following order in pinctrl-msm.c:
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1. pinctrl_register()
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2. gpiochip_add()
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3. gpiochip_add_pin_range()
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The actual error code -517 == -EPROBE_DEFER is coming from
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pinctrl_get_device_gpio_range(), which is called through:
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gpiochip_add
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of_gpiochip_add
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of_gpiochip_scan_gpios
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gpiod_hog
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gpiochip_request_own_desc
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__gpiod_request
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chip->request
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gpiochip_generic_request
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pinctrl_gpio_request
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pinctrl_get_device_gpio_range
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pinctrl_get_device_gpio_range() is unable to find any valid
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pin ranges, since nothing has been added to the pinctrldev_list yet.
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so the range can't be found, and the operation fails with -EPROBE_DEFER.
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This patch fixes the issue by adding the "gpio-ranges" property to
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the pinctrl device node of all upstream Qcom SoC. The pin ranges are
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then added by the gpio core.
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In order to remain compatible with older, existing DTs (and ACPI)
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a check for the "gpio-ranges" property has been added to
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msm_gpio_init(). This prevents the driver of adding the same entry
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to the pinctrldev_list twice.
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Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Origin: other, https://patchwork.kernel.org/patch/10339127/
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
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drivers/pinctrl/qcom/pinctrl-msm.c | 23 ++++++++++++++++++-----
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14 files changed, 32 insertions(+), 6 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -182,6 +182,7 @@
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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+ gpio-ranges = <&tlmm 0 0 100>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -839,11 +839,24 @@ static int msm_gpio_init(struct msm_pinc
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return ret;
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}
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- ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
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- if (ret) {
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- dev_err(pctrl->dev, "Failed to add pin range\n");
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- gpiochip_remove(&pctrl->chip);
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- return ret;
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+ /*
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+ * For DeviceTree-supported systems, the gpio core checks the
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+ * pinctrl's device node for the "gpio-ranges" property.
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+ * If it is present, it takes care of adding the pin ranges
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+ * for the driver. In this case the driver can skip ahead.
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+ *
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+ * In order to remain compatible with older, existing DeviceTree
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+ * files which don't set the "gpio-ranges" property or systems that
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+ * utilize ACPI the driver has to call gpiochip_add_pin_range().
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+ */
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+ if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
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+ ret = gpiochip_add_pin_range(&pctrl->chip,
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+ dev_name(pctrl->dev), 0, 0, chip->ngpio);
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+ if (ret) {
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+ dev_err(pctrl->dev, "Failed to add pin range\n");
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+ gpiochip_remove(&pctrl->chip);
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+ return ret;
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+ }
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}
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ret = gpiochip_irqchip_add(chip,
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