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3dd692cd6b
95672e04 broke booting secondary cores by removing 'qcom,saw' property
from L2 cache node. kpssv2_release_secondary() requires it.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
110 lines
3.1 KiB
Diff
110 lines
3.1 KiB
Diff
From 364123029d8d547336323fbd3d659ecd0bba913f Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Mon, 23 Jul 2018 08:41:02 +0200
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Subject: [PATCH 5/8] qcom: ipq4019: use v2 of the kpss bringup mechanism
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v1 was the incorrect choice here and sometimes the board
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would not come up properly.
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
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1 file changed, 17 insertions(+), 8 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -34,7 +34,8 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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reg = <0x0>;
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@@ -53,7 +54,8 @@
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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reg = <0x1>;
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@@ -64,7 +66,8 @@
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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reg = <0x2>;
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@@ -75,13 +78,20 @@
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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};
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ qcom,saw = <&saw_l2>;
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+ };
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};
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pmu {
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@@ -213,22 +223,22 @@
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};
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acc0: clock-controller@b088000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
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};
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acc1: clock-controller@b098000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
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};
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acc2: clock-controller@b0a8000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
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};
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acc3: clock-controller@b0b8000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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@@ -256,6 +266,12 @@
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regulator;
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};
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+ saw_l2: regulator@b012000 {
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+ compatible = "qcom,saw2";
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+ reg = <0xb012000 0x1000>;
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+ regulator;
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+ };
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+
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serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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