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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
61 lines
1.8 KiB
Diff
61 lines
1.8 KiB
Diff
From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Tue, 8 Nov 2022 15:23:57 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
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DT schema
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DT schema expects TLMM pin configuration nodes to be named with
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'-state' suffix and their optional children with '-pins' suffix.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -317,35 +317,35 @@
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interrupt-controller;
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#interrupt-cells = <0x2>;
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- serial_4_pins: serial4-pinmux {
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+ serial_4_pins: serial4-state {
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pins = "gpio23", "gpio24";
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function = "blsp4_uart1";
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drive-strength = <8>;
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bias-disable;
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};
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- i2c_0_pins: i2c-0-pinmux {
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+ i2c_0_pins: i2c-0-state {
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pins = "gpio42", "gpio43";
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function = "blsp1_i2c";
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drive-strength = <8>;
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bias-disable;
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};
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- spi_0_pins: spi-0-pins {
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+ spi_0_pins: spi-0-state {
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pins = "gpio38", "gpio39", "gpio40", "gpio41";
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function = "blsp0_spi";
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drive-strength = <8>;
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bias-disable;
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};
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- hsuart_pins: hsuart-pins {
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+ hsuart_pins: hsuart-state {
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pins = "gpio46", "gpio47", "gpio48", "gpio49";
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function = "blsp2_uart";
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drive-strength = <8>;
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bias-disable;
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};
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- qpic_pins: qpic-pins {
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+ qpic_pins: qpic-state {
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pins = "gpio1", "gpio3", "gpio4",
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"gpio5", "gpio6", "gpio7",
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"gpio8", "gpio10", "gpio11",
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