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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
From 0171978734227bdd7813bc6d805f609126e3849e Mon Sep 17 00:00:00 2001
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From: Johan Hovold <johan+linaro@kernel.org>
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Date: Tue, 5 Jul 2022 13:40:22 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq8074: drop USB PHY clock index
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The QMP USB PHY provides a single clock so drop the redundant clock
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index.
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Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -130,7 +130,7 @@
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<0x00058800 0x1f8>, /* PCS */
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<0x00058600 0x044>; /* PCS misc*/
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#phy-cells = <0>;
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- #clock-cells = <1>;
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+ #clock-cells = <0>;
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clocks = <&gcc GCC_USB1_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "gcc_usb1_pipe_clk_src";
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@@ -173,7 +173,7 @@
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<0x00078800 0x1f8>, /* PCS */
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<0x00078600 0x044>; /* PCS misc*/
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#phy-cells = <0>;
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- #clock-cells = <1>;
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+ #clock-cells = <0>;
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clocks = <&gcc GCC_USB0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "gcc_usb0_pipe_clk_src";
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