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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
48 lines
1.7 KiB
Diff
48 lines
1.7 KiB
Diff
From 18363f691e931abf0e9bdc9b5169fb15aa10224d Mon Sep 17 00:00:00 2001
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From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
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Date: Sun, 15 May 2022 03:24:22 +0530
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Subject: [PATCH] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names'
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for sdhci nodes
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Since the Qualcomm sdhci-msm device-tree binding has been converted
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to yaml format, 'make dtbs_check' reports a number of issues with
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ordering of 'clocks' & 'clock-names' for sdhci nodes:
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arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
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clock-names:0: 'iface' was expected
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arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
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clock-names:1: 'core' was expected
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arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
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clock-names:2: 'xo' was expected
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Fix the same by updating the offending 'dts' files.
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Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
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Cc: Rob Herring <robh@kernel.org>
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Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -384,10 +384,10 @@
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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- clocks = <&xo>,
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- <&gcc GCC_SDCC1_AHB_CLK>,
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- <&gcc GCC_SDCC1_APPS_CLK>;
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- clock-names = "xo", "iface", "core";
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+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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+ <&gcc GCC_SDCC1_APPS_CLK>,
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+ <&xo>;
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+ clock-names = "iface", "core", "xo";
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max-frequency = <384000000>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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