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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From ccc5b088058bccdf454bd296867c47e56c415cde Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Fri, 1 Oct 2021 22:54:21 +0800
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Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
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Add node to support the QUP5 I2C controller inside of IPQ8074.
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It is exactly the same as QUP2 controllers.
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Some routers like ZTE MF269 use this bus.
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20211001145421.18302-1-amadeus@jmu.edu.cn
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -430,6 +430,21 @@
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status = "disabled";
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};
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+ blsp1_i2c5: i2c@78b9000 {
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+ compatible = "qcom,i2c-qup-v2.2.1";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x78b9000 0x600>;
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+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
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+ clock-names = "iface", "core";
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+ clock-frequency = <400000>;
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+ dmas = <&blsp_dma 21>, <&blsp_dma 20>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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blsp1_i2c6: i2c@78ba000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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