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a911f63df9
Adjust the wrong phy-handle definitions for the sfp ports so that they
match the correct switch ports.
Fixes: 89eb8b50d1 ("realtek: dgs-1210-10mp: add full sfp description")
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
141 lines
2.7 KiB
Plaintext
141 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl83xx_d-link_dgs-1210_common.dtsi"
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#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
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/ {
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compatible = "d-link,dgs-1210-10mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc";
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model = "D-Link DGS-1210-10MP F";
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/* i2c for sfp port9 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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/* i2c for sfp port10 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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};
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&leds {
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link_act {
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label = "green:link_act";
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gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
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};
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poe {
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label = "green:poe";
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gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
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};
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poe_max {
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label = "yellow:poe_max";
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gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
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};
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};
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&keys {
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mode {
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label = "mode";
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gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_LIGHTS_TOGGLE>;
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};
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};
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&uart1 {
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status = "okay";
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(24)
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INTERNAL_PHY(26)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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port@24 {
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reg = <24>;
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label = "lan9";
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phy-handle = <&phy24>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan10";
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phy-handle = <&phy26>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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