mirror of
https://github.com/openwrt/openwrt.git
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f577cb25c0
The following patches were dropped because they are already applied
upstream:
- 0038-MIPS-lantiq-fpi-on-ar9.patch
- 0039-MIPS-lantiq-initialize-usb-on-boot.patch
- 0042-USB-DWC2-big-endian-support.patch
- 0043-gpio-stp-xway-fix-phy-mask.patch
All other patches were simply refreshed, except the following:
- 0001-MIPS-lantiq-add-pcie-driver.patch
Changes to arch/mips/lantiq/xway/sysctrl.c (these changes disabled
some PMU gates for the vrx200 / VR9 SoCs) were removed since the
upstream kernel disables unused PMU gates automatically (since
95135bfa7ead1becc2879230f72583dde2b71a0c
"MIPS: Lantiq: Deactivate most of the devices by default").
- 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
Since OpenWrt commit 55ba20afcc drivers
should use of_get_mac_address(). of_get_mac_address_mtd is not
available for drivers anymore since it's called automatically within
of_get_mac_address().
- 0028-NET-lantiq-various-etop-fixes.patch
Same changes as in 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
While refreshing the kernel configuration SPI support had to be moved to
config-4.4 because otherwise M25P80 was disabled.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48307
90 lines
2.6 KiB
Diff
90 lines
2.6 KiB
Diff
From aa705c1b0860da91f2ed1a4c0b57337e6de689e1 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 7 Aug 2014 18:55:31 +0200
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Subject: [PATCH 17/36] MTD: xway: fix nand locking
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/nand/xway_nand.c | 15 +++------------
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1 file changed, 3 insertions(+), 12 deletions(-)
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--- a/drivers/mtd/nand/xway_nand.c
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+++ b/drivers/mtd/nand/xway_nand.c
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@@ -80,13 +80,16 @@ static void xway_reset_chip(struct nand_
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static void xway_select_chip(struct mtd_info *mtd, int chip)
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{
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+ static unsigned long csflags;
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switch (chip) {
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case -1:
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ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
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ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
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+ spin_unlock_irqrestore(&ebu_lock, csflags);
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break;
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case 0:
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+ spin_lock_irqsave(&ebu_lock, csflags);
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ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
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ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
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break;
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@@ -99,7 +102,6 @@ static void xway_cmd_ctrl(struct mtd_inf
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{
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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- unsigned long flags;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_CLE)
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@@ -109,11 +111,9 @@ static void xway_cmd_ctrl(struct mtd_inf
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}
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if (cmd != NAND_CMD_NONE) {
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- spin_lock_irqsave(&ebu_lock, flags);
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writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
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while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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;
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- spin_unlock_irqrestore(&ebu_lock, flags);
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}
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}
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@@ -126,12 +126,9 @@ static unsigned char xway_read_byte(stru
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{
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
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- unsigned long flags;
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int ret;
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- spin_lock_irqsave(&ebu_lock, flags);
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ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
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- spin_unlock_irqrestore(&ebu_lock, flags);
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return ret;
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}
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@@ -140,26 +137,20 @@ static void xway_read_buf(struct mtd_inf
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{
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
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- unsigned long flags;
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int i;
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- spin_lock_irqsave(&ebu_lock, flags);
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for (i = 0; i < len; i++)
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buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
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- spin_unlock_irqrestore(&ebu_lock, flags);
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}
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static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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- unsigned long flags;
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int i;
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- spin_lock_irqsave(&ebu_lock, flags);
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for (i = 0; i < len; i++)
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ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA));
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- spin_unlock_irqrestore(&ebu_lock, flags);
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}
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static int xway_nand_probe(struct platform_device *pdev)
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