mirror of
https://github.com/openwrt/openwrt.git
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a9dda40fe2
Rebase patches and port SATA driver to work with Linux > 5.13. Tested on Shuttle KD-20. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
123 lines
3.9 KiB
Diff
123 lines
3.9 KiB
Diff
--- a/drivers/pci/controller/Kconfig
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+++ b/drivers/pci/controller/Kconfig
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@@ -312,6 +312,11 @@ config PCIE_HISI_ERR
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Say Y here if you want error handling support
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for the PCIe controller's errors on HiSilicon HIP SoCs
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+config PCIE_OXNAS
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+ bool "PLX Oxnas PCIe controller"
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+ depends on ARCH_OXNAS
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+ select PCIEPORTBUS
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+
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source "drivers/pci/controller/dwc/Kconfig"
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source "drivers/pci/controller/mobiveil/Kconfig"
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source "drivers/pci/controller/cadence/Kconfig"
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--- a/drivers/pci/controller/Makefile
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+++ b/drivers/pci/controller/Makefile
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@@ -33,6 +33,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
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obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
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obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
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+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
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obj-$(CONFIG_VMD) += vmd.o
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obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
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obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -289,7 +289,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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- ranges = <0 0x47000000 0x1000000>;
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+ ranges = <0 0x47000000 0x2000>;
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scu: scu@0 {
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compatible = "arm,arm11mp-scu";
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@@ -318,5 +318,86 @@
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<0x100 0x500>;
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};
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};
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+
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+ pcie0: pcie-controller@47c00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
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+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
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+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
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+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
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+
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+ bus-range = <0x00 0x7f>;
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+
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+ /* cfg inbound translator */
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+ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
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+ gpios = <&gpio1 12 0>;
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+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEA>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <2>;
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+ plxtech,pcie-ctrl-offset = <0x120>;
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+ plxtech,pcie-outbound-offset = <0x138>;
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+ status = "disabled";
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+ };
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+
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+ pcie1: pcie-controller@47e00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
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+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
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+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
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+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
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+
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+ bus-range = <0x80 0xff>;
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+
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+ /* cfg inbound translator */
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+ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
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+
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+ /* gpios = <&gpio1 12 0>; */
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+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEB>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <3>;
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+ plxtech,pcie-ctrl-offset = <0x124>;
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+ plxtech,pcie-outbound-offset = <0x174>;
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+ status = "disabled";
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+ };
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};
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};
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