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https://github.com/openwrt/openwrt.git
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9a1ec4d3f4
Copy files to kernel 5.4 to start porting. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
94 lines
2.7 KiB
Diff
94 lines
2.7 KiB
Diff
From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Tue, 19 Jul 2016 18:44:49 +0530
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Subject: PCI: qcom: Fixed IPQ806x specific clocks
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Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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---
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -85,6 +85,8 @@ struct qcom_pcie_resources_2_1_0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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struct clk *phy_clk;
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+ struct clk *aux_clk;
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+ struct clk *ref_clk;
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struct reset_control *pci_reset;
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struct reset_control *axi_reset;
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struct reset_control *ahb_reset;
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@@ -235,6 +237,14 @@ static int qcom_pcie_get_resources_2_1_0
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if (IS_ERR(res->phy_clk))
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return PTR_ERR(res->phy_clk);
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+ res->aux_clk = devm_clk_get(dev, "aux");
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+ if (IS_ERR(res->aux_clk))
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+ return PTR_ERR(res->aux_clk);
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+
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+ res->ref_clk = devm_clk_get(dev, "ref");
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+ if (IS_ERR(res->ref_clk))
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+ return PTR_ERR(res->ref_clk);
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+
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res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
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if (IS_ERR(res->pci_reset))
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return PTR_ERR(res->pci_reset);
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@@ -267,6 +277,8 @@ static void qcom_pcie_deinit_2_1_0(struc
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clk_disable_unprepare(res->iface_clk);
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clk_disable_unprepare(res->core_clk);
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clk_disable_unprepare(res->phy_clk);
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+ clk_disable_unprepare(res->aux_clk);
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+ clk_disable_unprepare(res->ref_clk);
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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}
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@@ -296,16 +308,28 @@ static int qcom_pcie_init_2_1_0(struct q
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goto err_assert_ahb;
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}
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+ ret = clk_prepare_enable(res->core_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable core clock\n");
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+ goto err_clk_core;
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+ }
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+
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ret = clk_prepare_enable(res->phy_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable phy clock\n");
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goto err_clk_phy;
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}
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- ret = clk_prepare_enable(res->core_clk);
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+ ret = clk_prepare_enable(res->aux_clk);
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if (ret) {
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- dev_err(dev, "cannot prepare/enable core clock\n");
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- goto err_clk_core;
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+ dev_err(dev, "cannot prepare/enable aux clock\n");
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+ goto err_clk_aux;
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+ }
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+
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+ ret = clk_prepare_enable(res->ref_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable ref clock\n");
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+ goto err_clk_ref;
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}
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ret = reset_control_deassert(res->ahb_reset);
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@@ -361,10 +385,14 @@ static int qcom_pcie_init_2_1_0(struct q
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return 0;
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err_deassert_ahb:
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- clk_disable_unprepare(res->core_clk);
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-err_clk_core:
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+ clk_disable_unprepare(res->ref_clk);
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+err_clk_ref:
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+ clk_disable_unprepare(res->aux_clk);
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+err_clk_aux:
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clk_disable_unprepare(res->phy_clk);
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err_clk_phy:
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+ clk_disable_unprepare(res->core_clk);
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+err_clk_core:
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clk_disable_unprepare(res->iface_clk);
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err_assert_ahb:
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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