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60c1fe6928
Add support for the FriendlyARM NanoPi R2C. Manually generated of-platdata files to avoid swig dependency. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
200 lines
5.6 KiB
Diff
200 lines
5.6 KiB
Diff
From 7000a609473ffe14d32c656cdd0ff3ca0d3ecbd7 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Tue, 11 Apr 2023 18:14:49 +0800
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Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
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The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
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chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
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The device tree is taken from the kernel linux-next branch:
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https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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---
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arch/arm/dts/Makefile | 1 +
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arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi | 3 +
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arch/arm/dts/rk3328-nanopi-r2c.dts | 40 ++++++++
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board/rockchip/evb_rk3328/MAINTAINERS | 6 ++
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configs/nanopi-r2c-rk3328_defconfig | 112 +++++++++++++++++++++
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5 files changed, 162 insertions(+)
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create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts
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create mode 100644 configs/nanopi-r2c-rk3328_defconfig
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
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dtb-$(CONFIG_ROCKCHIP_RK3328) += \
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rk3328-evb.dtb \
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+ rk3328-nanopi-r2c.dtb \
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rk3328-nanopi-r2s.dtb \
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rk3328-roc-cc.dtb \
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rk3328-rock64.dtb \
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
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@@ -0,0 +1,3 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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+
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+#include "rk3328-nanopi-r2s-u-boot.dtsi"
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
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@@ -0,0 +1,40 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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+ * (http://www.friendlyarm.com)
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+ *
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+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
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+ */
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+
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+/dts-v1/;
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+#include "rk3328-nanopi-r2s.dts"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R2C";
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+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
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+};
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+
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+&gmac2io {
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+ phy-handle = <&yt8521s>;
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+ tx_delay = <0x22>;
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+ rx_delay = <0x12>;
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+
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+ mdio {
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+ /delete-node/ ethernet-phy@1;
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+
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+ yt8521s: ethernet-phy@3 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <3>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <10000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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--- a/board/rockchip/evb_rk3328/MAINTAINERS
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+++ b/board/rockchip/evb_rk3328/MAINTAINERS
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@@ -5,6 +5,12 @@ F: board/rockchip/evb_rk3328
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F: include/configs/evb_rk3328.h
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F: configs/evb-rk3328_defconfig
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+NANOPI-R2C-RK3328
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+M: Tianling Shen <cnsztl@gmail.com>
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+S: Maintained
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+F: configs/nanopi-r2c-rk3328_defconfig
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+F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
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+
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NANOPI-R2S-RK3328
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M: David Bauer <mail@david-bauer.net>
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S: Maintained
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--- /dev/null
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+++ b/configs/nanopi-r2c-rk3328_defconfig
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@@ -0,0 +1,98 @@
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+CONFIG_ARM=y
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_SYS_TEXT_BASE=0x00200000
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+CONFIG_SPL_GPIO_SUPPORT=y
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+CONFIG_NR_DRAM_BANKS=1
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+CONFIG_ENV_OFFSET=0x3F8000
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+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
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+CONFIG_ROCKCHIP_RK3328=y
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+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
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+CONFIG_TPL_LIBCOMMON_SUPPORT=y
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+CONFIG_TPL_LIBGENERIC_SUPPORT=y
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+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
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+CONFIG_SPL_STACK_R_ADDR=0x600000
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+CONFIG_DEBUG_UART_BASE=0xFF130000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_DEBUG_UART=y
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+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
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+# CONFIG_ANDROID_BOOT_IMAGE is not set
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_MISC_INIT_R=y
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
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+CONFIG_SPL_STACK_R=y
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+CONFIG_SPL_I2C_SUPPORT=y
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+CONFIG_SPL_POWER_SUPPORT=y
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+CONFIG_SPL_ATF=y
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+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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+CONFIG_CMD_BOOTZ=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_USB=y
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+# CONFIG_CMD_SETEXPR is not set
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+CONFIG_CMD_TIME=y
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_TPL_OF_CONTROL=y
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+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_TPL_OF_PLATDATA=y
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+CONFIG_ENV_IS_IN_MMC=y
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+CONFIG_NET_RANDOM_ETHADDR=y
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+CONFIG_TPL_DM=y
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+CONFIG_REGMAP=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_TPL_REGMAP=y
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+CONFIG_SYSCON=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_TPL_SYSCON=y
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+CONFIG_CLK=y
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+CONFIG_SPL_CLK=y
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+CONFIG_FASTBOOT_BUF_ADDR=0x800800
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+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_SF_DEFAULT_SPEED=20000000
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+CONFIG_DM_ETH=y
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_PINCTRL=y
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+CONFIG_SPL_PINCTRL=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_SPL_DM_REGULATOR=y
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+CONFIG_REGULATOR_PWM=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_SPL_DM_REGULATOR_FIXED=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_RAM=y
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+CONFIG_SPL_RAM=y
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+CONFIG_TPL_RAM=y
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+CONFIG_DM_RESET=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYSINFO=y
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+CONFIG_SYSRESET=y
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+# CONFIG_TPL_SYSRESET is not set
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_XHCI_DWC3=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_OHCI_GENERIC=y
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+CONFIG_USB_DWC2=y
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+CONFIG_USB_DWC3=y
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+# CONFIG_USB_DWC3_GADGET is not set
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+CONFIG_USB_GADGET=y
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+CONFIG_USB_GADGET_DWC2_OTG=y
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+CONFIG_SPL_TINY_MEMSET=y
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+CONFIG_TPL_TINY_MEMSET=y
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+CONFIG_ERRNO_STR=y
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