mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
4e39949dd1
Removed since could be reverse-applied by quilt and found to be included upstream: backport-5.4/789-net-usb-qmi_wwan-Set-DTR-quirk-for-MR400.patch All modifications made by update_kernel.sh Build system: x86_64 Build-tested: ipq806x/R7800, bcm27xx/bcm2711, ath79/generic Run-tested: ipq806x/R7800 No dmesg regressions, everything functional Signed-off-by: John Audia <graysky@archlinux.us> Tested-by: Curtis Deptuck <curtdept@me.com> [x86_64 build/run]
66 lines
2.7 KiB
Diff
66 lines
2.7 KiB
Diff
From 094a648bc2217a9624f35224059c3eac86196143 Mon Sep 17 00:00:00 2001
|
|
From: Joakim Zhang <qiangqing.zhang@nxp.com>
|
|
Date: Fri, 12 Jul 2019 08:02:51 +0000
|
|
Subject: [PATCH] can: flexcan: add ISO CAN FD feature support
|
|
|
|
ISO CAN FD is introduced to increase the failture detection capability
|
|
than non-ISO CAN FD. The non-ISO CAN FD is still supported by FlexCAN so
|
|
that it can be used mainly during an intermediate phase, for evaluation
|
|
and development purposes.
|
|
|
|
Therefore, it is strongly recommended to configure FlexCAN to the ISO
|
|
CAN FD protocol by setting the ISOCANFDEN field in the CTRL2 register.
|
|
|
|
NOTE: If you only set "fd on", driver will use ISO FD mode by default.
|
|
You should set "fd-non-iso on" after setting "fd on" if you want to use
|
|
NON ISO FD mode.
|
|
|
|
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
|
|
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
|
|
---
|
|
drivers/net/can/flexcan.c | 8 +++++++-
|
|
1 file changed, 7 insertions(+), 1 deletion(-)
|
|
|
|
--- a/drivers/net/can/flexcan.c
|
|
+++ b/drivers/net/can/flexcan.c
|
|
@@ -92,6 +92,7 @@
|
|
#define FLEXCAN_CTRL2_MRP BIT(18)
|
|
#define FLEXCAN_CTRL2_RRS BIT(17)
|
|
#define FLEXCAN_CTRL2_EACEN BIT(16)
|
|
+#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
|
|
|
|
/* FLEXCAN memory error control register (MECR) bits */
|
|
#define FLEXCAN_MECR_ECRWRDIS BIT(31)
|
|
@@ -1324,6 +1325,7 @@ static int flexcan_chip_start(struct net
|
|
reg_fdctrl = priv->read(®s->fdctrl) & ~FLEXCAN_FDCTRL_FDRATE;
|
|
reg_fdctrl &= ~(FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3));
|
|
reg_mcr = priv->read(®s->mcr) & ~FLEXCAN_MCR_FDEN;
|
|
+ reg_ctrl2 = priv->read(®s->ctrl2) & ~FLEXCAN_CTRL2_ISOCANFDEN;
|
|
|
|
/* support BRS when set CAN FD mode
|
|
* 64 bytes payload per MB and 7 MBs per RAM block by default
|
|
@@ -1333,10 +1335,14 @@ static int flexcan_chip_start(struct net
|
|
reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
|
|
reg_fdctrl |= FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3);
|
|
reg_mcr |= FLEXCAN_MCR_FDEN;
|
|
+
|
|
+ if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
|
|
+ reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
|
|
}
|
|
|
|
priv->write(reg_fdctrl, ®s->fdctrl);
|
|
priv->write(reg_mcr, ®s->mcr);
|
|
+ priv->write(reg_ctrl2, ®s->ctrl2);
|
|
}
|
|
|
|
if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
|
|
@@ -1856,7 +1862,7 @@ static int flexcan_probe(struct platform
|
|
|
|
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_TIMESTAMP_SUPPORT_FD) {
|
|
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
|
|
- priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
|
|
+ priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO;
|
|
priv->can.bittiming_const = &flexcan_fd_bittiming_const;
|
|
priv->can.data_bittiming_const = &flexcan_fd_data_bittiming_const;
|
|
} else {
|