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https://github.com/openwrt/openwrt.git
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76d1168d0d
Ran update_kernel.sh in a fresh clone without any existing toolchains.
No manual changes needed.
Build system: x86_64
Build-tested: bcm27xx/bcm2711
Signed-off-by: John Audia <graysky@archlinux.us>
(cherry-picked from commit 5d3a6fd970)
232 lines
7.5 KiB
Diff
232 lines
7.5 KiB
Diff
From 3426e5e4339f124f00eef8815b56a80481364550 Mon Sep 17 00:00:00 2001
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From: Po Liu <po.liu@nxp.com>
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Date: Mon, 25 Nov 2019 05:56:56 +0000
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Subject: [PATCH] enetc: add support Credit Based Shaper(CBS) for hardware
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offload
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The ENETC hardware support the Credit Based Shaper(CBS) which part
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of the IEEE-802.1Qav. The CBS driver was loaded by the sch_cbs
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interface when set in the QOS in the kernel.
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Here is an example command to set 20Mbits bandwidth in 1Gbits port
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for taffic class 7:
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tc qdisc add dev eth0 root handle 1: mqprio \
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num_tc 8 map 0 1 2 3 4 5 6 7 hw 1
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tc qdisc replace dev eth0 parent 1:8 cbs \
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locredit -1470 hicredit 30 \
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sendslope -980000 idleslope 20000 offload 1
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Signed-off-by: Po Liu <Po.Liu@nxp.com>
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Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
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Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/freescale/enetc/Kconfig | 4 +-
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drivers/net/ethernet/freescale/enetc/enetc.c | 2 +
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drivers/net/ethernet/freescale/enetc/enetc.h | 2 +
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drivers/net/ethernet/freescale/enetc/enetc_hw.h | 4 +
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drivers/net/ethernet/freescale/enetc/enetc_qos.c | 128 +++++++++++++++++++++++
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5 files changed, 138 insertions(+), 2 deletions(-)
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--- a/drivers/net/ethernet/freescale/enetc/Kconfig
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+++ b/drivers/net/ethernet/freescale/enetc/Kconfig
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@@ -53,10 +53,10 @@ config FSL_ENETC_HW_TIMESTAMPING
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config FSL_ENETC_QOS
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bool "ENETC hardware Time-sensitive Network support"
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- depends on (FSL_ENETC || FSL_ENETC_VF) && NET_SCH_TAPRIO
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+ depends on (FSL_ENETC || FSL_ENETC_VF) && (NET_SCH_TAPRIO || NET_SCH_CBS)
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help
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There are Time-Sensitive Network(TSN) capabilities(802.1Qbv/802.1Qci
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/802.1Qbu etc.) supported by ENETC. These TSN capabilities can be set
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enable/disable from user space via Qos commands(tc). In the kernel
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side, it can be loaded by Qos driver. Currently, it is only support
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- taprio(802.1Qbv).
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+ taprio(802.1Qbv) and Credit Based Shaper(802.1Qbu).
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--- a/drivers/net/ethernet/freescale/enetc/enetc.c
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+++ b/drivers/net/ethernet/freescale/enetc/enetc.c
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@@ -1524,6 +1524,8 @@ int enetc_setup_tc(struct net_device *nd
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return enetc_setup_tc_mqprio(ndev, type_data);
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case TC_SETUP_QDISC_TAPRIO:
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return enetc_setup_tc_taprio(ndev, type_data);
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+ case TC_SETUP_QDISC_CBS:
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+ return enetc_setup_tc_cbs(ndev, type_data);
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default:
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return -EOPNOTSUPP;
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}
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--- a/drivers/net/ethernet/freescale/enetc/enetc.h
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+++ b/drivers/net/ethernet/freescale/enetc/enetc.h
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@@ -255,7 +255,9 @@ int enetc_send_cmd(struct enetc_si *si,
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#ifdef CONFIG_FSL_ENETC_QOS
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int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data);
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void enetc_sched_speed_set(struct net_device *ndev);
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+int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data);
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#else
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#define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP
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#define enetc_sched_speed_set(ndev) (void)0
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+#define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP
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#endif
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--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
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+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
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@@ -185,6 +185,8 @@ enum enetc_bdr_type {TX, RX};
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#define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
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#define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
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+#define ENETC_CBSE BIT(31)
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+#define ENETC_CBS_BW_MASK GENMASK(6, 0)
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#define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
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#define ENETC_RSSHASH_KEY_SIZE 40
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#define ENETC_PRSSCAPR 0x1404
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@@ -679,6 +681,8 @@ struct enetc_cbd {
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u8 status_flags;
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};
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+#define ENETC_CLK 400000000ULL
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+
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/* port time gating control register */
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#define ENETC_QBV_PTGCR_OFFSET 0x11a00
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#define ENETC_QBV_TGE BIT(31)
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--- a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
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+++ b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
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@@ -4,6 +4,7 @@
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#include "enetc.h"
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#include <net/pkt_sched.h>
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+#include <linux/math64.h>
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static u16 enetc_get_max_gcl_len(struct enetc_hw *hw)
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{
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@@ -170,3 +171,130 @@ int enetc_setup_tc_taprio(struct net_dev
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return err;
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}
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+
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+static u32 enetc_get_cbs_enable(struct enetc_hw *hw, u8 tc)
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+{
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+ return enetc_port_rd(hw, ENETC_PTCCBSR0(tc)) & ENETC_CBSE;
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+}
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+
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+static u8 enetc_get_cbs_bw(struct enetc_hw *hw, u8 tc)
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+{
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+ return enetc_port_rd(hw, ENETC_PTCCBSR0(tc)) & ENETC_CBS_BW_MASK;
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+}
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+
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+int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data)
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+{
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+ struct enetc_ndev_priv *priv = netdev_priv(ndev);
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+ struct tc_cbs_qopt_offload *cbs = type_data;
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+ u32 port_transmit_rate = priv->speed;
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+ u8 tc_nums = netdev_get_num_tc(ndev);
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+ struct enetc_si *si = priv->si;
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+ u32 hi_credit_bit, hi_credit_reg;
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+ u32 max_interference_size;
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+ u32 port_frame_max_size;
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+ u32 tc_max_sized_frame;
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+ u8 tc = cbs->queue;
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+ u8 prio_top, prio_next;
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+ int bw_sum = 0;
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+ u8 bw;
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+
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+ prio_top = netdev_get_prio_tc_map(ndev, tc_nums - 1);
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+ prio_next = netdev_get_prio_tc_map(ndev, tc_nums - 2);
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+
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+ /* Support highest prio and second prio tc in cbs mode */
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+ if (tc != prio_top && tc != prio_next)
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+ return -EOPNOTSUPP;
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+
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+ if (!cbs->enable) {
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+ /* Make sure the other TC that are numerically
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+ * lower than this TC have been disabled.
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+ */
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+ if (tc == prio_top &&
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+ enetc_get_cbs_enable(&si->hw, prio_next)) {
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+ dev_err(&ndev->dev,
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+ "Disable TC%d before disable TC%d\n",
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+ prio_next, tc);
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+ return -EINVAL;
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+ }
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+
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+ enetc_port_wr(&si->hw, ENETC_PTCCBSR1(tc), 0);
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+ enetc_port_wr(&si->hw, ENETC_PTCCBSR0(tc), 0);
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+
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+ return 0;
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+ }
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+
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+ if (cbs->idleslope - cbs->sendslope != port_transmit_rate * 1000L ||
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+ cbs->idleslope < 0 || cbs->sendslope > 0)
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+ return -EOPNOTSUPP;
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+
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+ port_frame_max_size = ndev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
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+
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+ bw = cbs->idleslope / (port_transmit_rate * 10UL);
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+
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+ /* Make sure the other TC that are numerically
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+ * higher than this TC have been enabled.
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+ */
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+ if (tc == prio_next) {
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+ if (!enetc_get_cbs_enable(&si->hw, prio_top)) {
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+ dev_err(&ndev->dev,
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+ "Enable TC%d first before enable TC%d\n",
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+ prio_top, prio_next);
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+ return -EINVAL;
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+ }
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+ bw_sum += enetc_get_cbs_bw(&si->hw, prio_top);
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+ }
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+
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+ if (bw_sum + bw >= 100) {
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+ dev_err(&ndev->dev,
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+ "The sum of all CBS Bandwidth can't exceed 100\n");
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+ return -EINVAL;
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+ }
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+
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+ tc_max_sized_frame = enetc_port_rd(&si->hw, ENETC_PTCMSDUR(tc));
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+
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+ /* For top prio TC, the max_interfrence_size is maxSizedFrame.
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+ *
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+ * For next prio TC, the max_interfrence_size is calculated as below:
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+ *
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+ * max_interference_size = M0 + Ma + Ra * M0 / (R0 - Ra)
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+ *
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+ * - RA: idleSlope for AVB Class A
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+ * - R0: port transmit rate
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+ * - M0: maximum sized frame for the port
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+ * - MA: maximum sized frame for AVB Class A
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+ */
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+
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+ if (tc == prio_top) {
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+ max_interference_size = port_frame_max_size * 8;
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+ } else {
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+ u32 m0, ma, r0, ra;
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+
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+ m0 = port_frame_max_size * 8;
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+ ma = enetc_port_rd(&si->hw, ENETC_PTCMSDUR(prio_top)) * 8;
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+ ra = enetc_get_cbs_bw(&si->hw, prio_top) *
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+ port_transmit_rate * 10000ULL;
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+ r0 = port_transmit_rate * 1000000ULL;
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+ max_interference_size = m0 + ma +
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+ (u32)div_u64((u64)ra * m0, r0 - ra);
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+ }
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+
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+ /* hiCredit bits calculate by:
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+ *
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+ * maxSizedFrame * (idleSlope/portTxRate)
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+ */
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+ hi_credit_bit = max_interference_size * bw / 100;
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+
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+ /* hiCredit bits to hiCredit register need to calculated as:
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+ *
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+ * (enetClockFrequency / portTransmitRate) * 100
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+ */
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+ hi_credit_reg = (u32)div_u64((ENETC_CLK * 100ULL) * hi_credit_bit,
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+ port_transmit_rate * 1000000ULL);
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+
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+ enetc_port_wr(&si->hw, ENETC_PTCCBSR1(tc), hi_credit_reg);
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+
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+ /* Set bw register and enable this traffic class */
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+ enetc_port_wr(&si->hw, ENETC_PTCCBSR0(tc), bw | ENETC_CBSE);
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+
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+ return 0;
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+}
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