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https://github.com/openwrt/openwrt.git
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7f3dab2fc3
Refreshed all patches. Removed upstream ramips patch: 0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch Compile-tested: ar71xx Run-tested: ar71xx Signed-off-by: Etienne Haarsma <bladeoner112@gmail.com> Tested-by: Stijn Segers <francesco.borromini@inventati.org>
261 lines
9.1 KiB
Diff
261 lines
9.1 KiB
Diff
From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 15 May 2014 00:29:18 -0700
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Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr
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Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
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The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
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to this function.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +-
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drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++---------
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drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++-
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3 files changed, 58 insertions(+), 26 deletions(-)
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--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
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+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
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@@ -2165,7 +2165,7 @@ static s32 igb_read_phy_reg_82580(struct
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if (ret_val)
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goto out;
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- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
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hw->phy.ops.release(hw);
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@@ -2190,7 +2190,7 @@ static s32 igb_write_phy_reg_82580(struc
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if (ret_val)
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goto out;
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- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
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hw->phy.ops.release(hw);
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--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
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+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
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@@ -130,9 +130,8 @@ out:
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* Reads the MDI control regsiter in the PHY at offset and stores the
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* information read to data.
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**/
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-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
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{
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- struct e1000_phy_info *phy = &hw->phy;
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u32 i, mdicnfg, mdic = 0;
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s32 ret_val = 0;
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@@ -151,14 +150,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
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case e1000_i211:
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mdicnfg = rd32(E1000_MDICNFG);
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mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
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+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
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wr32(E1000_MDICNFG, mdicnfg);
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mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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(E1000_MDIC_OP_READ));
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break;
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default:
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mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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- (phy->addr << E1000_MDIC_PHY_SHIFT) |
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+ (addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_READ));
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break;
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}
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@@ -212,9 +211,8 @@ out:
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*
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* Writes data to MDI control register in the PHY at offset.
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**/
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-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
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{
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- struct e1000_phy_info *phy = &hw->phy;
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u32 i, mdicnfg, mdic = 0;
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s32 ret_val = 0;
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@@ -233,7 +231,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
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case e1000_i211:
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mdicnfg = rd32(E1000_MDICNFG);
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mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
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+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
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wr32(E1000_MDICNFG, mdicnfg);
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mdic = (((u32)data) |
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(offset << E1000_MDIC_REG_SHIFT) |
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@@ -242,7 +240,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
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default:
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mdic = (((u32)data) |
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(offset << E1000_MDIC_REG_SHIFT) |
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- (phy->addr << E1000_MDIC_PHY_SHIFT) |
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+ (addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_WRITE));
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break;
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}
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@@ -462,7 +460,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
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goto out;
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if (offset > MAX_PHY_MULTI_PAGE_REG) {
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- ret_val = igb_write_phy_reg_mdic(hw,
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
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IGP01E1000_PHY_PAGE_SELECT,
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(u16)offset);
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if (ret_val) {
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@@ -471,8 +469,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
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}
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}
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- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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- data);
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+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
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+ MAX_PHY_REG_ADDRESS & offset, data);
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hw->phy.ops.release(hw);
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@@ -501,7 +499,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
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goto out;
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if (offset > MAX_PHY_MULTI_PAGE_REG) {
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- ret_val = igb_write_phy_reg_mdic(hw,
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
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IGP01E1000_PHY_PAGE_SELECT,
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(u16)offset);
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if (ret_val) {
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@@ -510,8 +508,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
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}
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}
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- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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- data);
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
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+ MAX_PHY_REG_ADDRESS & offset, data);
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hw->phy.ops.release(hw);
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@@ -2551,8 +2549,9 @@ out:
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}
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/**
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- * igb_write_phy_reg_gs40g - Write GS40G PHY register
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+ * igb_write_reg_gs40g - Write GS40G PHY register
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* @hw: pointer to the HW structure
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+ * @addr: phy address to write to
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* @offset: lower half is register offset to write to
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* upper half is page to use.
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* @data: data to write at register offset
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@@ -2560,7 +2559,7 @@ out:
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* Acquires semaphore, if necessary, then writes the data to PHY register
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* at the offset. Release any acquired semaphores before exiting.
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**/
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-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
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+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
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{
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s32 ret_val;
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u16 page = offset >> GS40G_PAGE_SHIFT;
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@@ -2570,10 +2569,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
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if (ret_val)
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return ret_val;
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- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
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+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
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if (ret_val)
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goto release;
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- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
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release:
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hw->phy.ops.release(hw);
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@@ -2581,8 +2580,24 @@ release:
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}
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/**
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- * igb_read_phy_reg_gs40g - Read GS40G PHY register
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+ * igb_write_phy_reg_gs40g - Write GS40G PHY register
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+ * @hw: pointer to the HW structure
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+ * @offset: lower half is register offset to write to
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+ * upper half is page to use.
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+ * @data: data to write at register offset
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+ *
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+ * Acquires semaphore, if necessary, then writes the data to PHY register
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+ * at the offset. Release any acquired semaphores before exiting.
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+ **/
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+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
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+{
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+ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
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+}
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+
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+/**
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+ * igb_read_reg_gs40g - Read GS40G PHY register
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* @hw: pointer to the HW structure
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+ * @addr: phy address to read from
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* @offset: lower half is register offset to read to
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* upper half is page to use.
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* @data: data to read at register offset
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@@ -2590,7 +2605,7 @@ release:
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* Acquires semaphore, if necessary, then reads the data in the PHY register
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* at the offset. Release any acquired semaphores before exiting.
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**/
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-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
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+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
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{
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s32 ret_val;
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u16 page = offset >> GS40G_PAGE_SHIFT;
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@@ -2600,10 +2615,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
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if (ret_val)
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return ret_val;
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- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
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+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
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if (ret_val)
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goto release;
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- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
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release:
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hw->phy.ops.release(hw);
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@@ -2611,6 +2626,21 @@ release:
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}
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/**
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+ * igb_read_phy_reg_gs40g - Read GS40G PHY register
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+ * @hw: pointer to the HW structure
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+ * @offset: lower half is register offset to read to
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+ * upper half is page to use.
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+ * @data: data to read at register offset
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+ *
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+ * Acquires semaphore, if necessary, then reads the data in the PHY register
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+ * at the offset. Release any acquired semaphores before exiting.
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+ **/
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+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
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+{
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+ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
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+}
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+
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+/**
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* igb_set_master_slave_mode - Setup PHY for Master/slave mode
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* @hw: pointer to the HW structure
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*
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--- a/drivers/net/ethernet/intel/igb/e1000_phy.h
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+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
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@@ -62,8 +62,8 @@ void igb_power_up_phy_copper(struct e100
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void igb_power_down_phy_copper(struct e1000_hw *hw);
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s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
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s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);
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-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
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-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
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+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
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+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
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s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
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s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
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@@ -73,6 +73,8 @@ s32 igb_phy_force_speed_duplex_82580(st
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s32 igb_get_cable_length_82580(struct e1000_hw *hw);
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s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
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+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
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+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
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s32 igb_check_polarity_m88(struct e1000_hw *hw);
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/* IGP01E1000 Specific Registers */
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