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659f4a13dd
With Linux 6.1 many of our downstream patches and out-of-tree files can be removed or at least replaced by backported upstream commits. Signed-off-by: Daniel Golle <daniel@makrotopia.org> [fix CMDLINE_OVERRIDE for arm64] Signed-off-by: Bjørn Mork <bjorn@mork.no>
114 lines
4.5 KiB
C
114 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include "clk-mux.h"
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#include "clk-pll.h"
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#define MT7988_PLL_FMAX (2500UL * MHZ)
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#define MT7988_PCW_CHG_SHIFT 2
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#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
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_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \
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_div_table) \
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{ \
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.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, .flags = _flags, \
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.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \
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.pcwbits = _pcwbits, .pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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.pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \
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.div_table = _div_table, .parent_name = "clkxtal", \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
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_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \
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PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
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_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
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0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
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PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
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23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
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HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
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0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
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PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
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HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
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PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
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(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
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0x0154),
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PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
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0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
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PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
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0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
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PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
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(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
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0x0204),
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PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
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HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
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PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
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HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
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32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
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};
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static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
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{ .compatible = "mediatek,mt7988-apmixedsys", },
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{ /* sentinel */ }
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};
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static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
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if (!clk_data)
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return -ENOMEM;
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mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r) {
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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goto free_apmixed_data;
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}
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return r;
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free_apmixed_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static struct platform_driver clk_mt7988_apmixed_drv = {
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.probe = clk_mt7988_apmixed_probe,
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.driver = {
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.name = "clk-mt7988-apmixed",
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.of_match_table = of_match_clk_mt7988_apmixed,
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},
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};
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builtin_platform_driver(clk_mt7988_apmixed_drv);
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MODULE_LICENSE("GPL");
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