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b4ed8a9275
Removed upstreamed: generic/backport-5.4/070-v5.5-MIPS-BPF-Restore-MIPS32-cBPF-JIT.patch All others updated automatically. Compile-tested on: lantiq/xrx200, armvirt/64 Runtime-tested on: lantiq/xrx200, armvirt/64 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
72 lines
2.8 KiB
Diff
72 lines
2.8 KiB
Diff
From 25291f86f449c4488a0a46b1e6b3ce3b83dbf1f9 Mon Sep 17 00:00:00 2001
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From: Xiaowei Bao <xiaowei.bao@nxp.com>
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Date: Wed, 15 May 2019 10:14:30 +0800
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Subject: [PATCH] arm64: dts: ls1028a: Add PCIe controller DT nodes
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LS1028a implements 2 PCIe 3.0 controllers.
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Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 50 ++++++++++++++++++++++++++
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1 file changed, 50 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@@ -649,6 +649,56 @@
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};
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};
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+ pcie@3400000 {
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+ compatible = "fsl,ls1028a-pcie";
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+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
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+ reg-names = "regs", "config";
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+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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+ interrupt-names = "pme", "aer";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
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+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pcie@3500000 {
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+ compatible = "fsl,ls1028a-pcie";
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+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
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+ reg-names = "regs", "config";
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+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pme", "aer";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
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+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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pcie@1f0000000 { /* Integrated Endpoint Root Complex */
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compatible = "pci-host-ecam-generic";
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reg = <0x01 0xf0000000 0x0 0x100000>;
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