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167 lines
5.6 KiB
C
167 lines
5.6 KiB
C
#ifndef __AR531X_H
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#define __AR531X_H
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#include <asm/cpu-info.h>
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#include <ar531x_platform.h>
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#include "ar5312/ar5312.h"
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#include "ar5315/ar5315.h"
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/*
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* C access to CLZ instruction
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* (count leading zeroes).
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*/
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static inline int clz(unsigned long val)
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{
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int ret;
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__asm__ volatile (
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".set\tnoreorder\n\t"
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".set\tnoat\n\t"
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".set\tmips32\n\t"
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"clz\t%0,%1\n\t"
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".set\tmips0\n\t"
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".set\tat\n\t"
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".set\treorder"
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: "=r" (ret)
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: "r" (val)
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);
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return ret;
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}
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/*
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* Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
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* using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
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*/
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#ifdef CONFIG_ATHEROS_AR5312
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#define DO_AR5312(...) \
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if (current_cpu_data.cputype != CPU_4KEC) { \
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__VA_ARGS__ \
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}
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#else
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#define DO_AR5312(...)
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#endif
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#ifdef CONFIG_ATHEROS_AR5315
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#define DO_AR5315(...) \
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if (current_cpu_data.cputype == CPU_4KEC) { \
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__VA_ARGS__ \
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}
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#else
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#define DO_AR5315(...)
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#endif
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#define AR531X_MISC_IRQ_BASE 0x20
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#define AR531X_GPIO_IRQ_BASE 0x30
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/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
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#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
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#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
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/* Miscellaneous interrupts, which share IP6 */
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#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
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#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
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#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
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#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
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#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
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#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
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#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
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#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
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#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
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#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
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#define AR531X_MISC_IRQ_COUNT 10
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/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
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#define AR531X_GPIO_IRQ_NONE AR531X_MISC_IRQ_BASE+0
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#define AR531X_GPIO_IRQ(n) AR531X_MISC_IRQ_BASE+(n)+1
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#define AR531X_GPIO_IRQ_COUNT 22
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#define sysRegRead(phys) \
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(*(volatile u32 *)KSEG1ADDR(phys))
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#define sysRegWrite(phys, val) \
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((*(volatile u32 *)KSEG1ADDR(phys)) = (val))
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/*
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* This is board-specific data that is stored in a "fixed" location in flash.
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* It is shared across operating systems, so it should not be changed lightly.
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* The main reason we need it is in order to extract the ethernet MAC
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* address(es).
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*/
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struct ar531x_boarddata {
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u32 magic; /* board data is valid */
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#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
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u16 cksum; /* checksum (starting with BD_REV 2) */
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u16 rev; /* revision of this struct */
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#define BD_REV 4
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char boardName[64]; /* Name of board */
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u16 major; /* Board major number */
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u16 minor; /* Board minor number */
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u32 config; /* Board configuration */
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#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
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#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
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#define BD_UART1 0x00000004 /* UART1 is stuffed */
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#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
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#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
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#define BD_SYSLED 0x00000020 /* System LED stuffed */
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#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
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#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
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#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
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#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
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#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
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#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
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#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
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#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
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#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
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#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
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#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
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#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
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u16 resetConfigGpio; /* Reset factory GPIO pin */
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u16 sysLedGpio; /* System LED GPIO pin */
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u32 cpuFreq; /* CPU core frequency in Hz */
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u32 sysFreq; /* System frequency in Hz */
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u32 cntFreq; /* Calculated C0_COUNT frequency */
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u8 wlan0Mac[6];
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u8 enet0Mac[6];
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u8 enet1Mac[6];
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u16 pciId; /* Pseudo PCIID for common code */
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u16 memCap; /* cap bank1 in MB */
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/* version 3 */
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u8 wlan1Mac[6]; /* (ar5212) */
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};
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#define BOARD_CONFIG_BUFSZ 0x1000
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extern char *board_config, *radio_config;
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extern void serial_setup(unsigned long mapbase, unsigned int uartclk);
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extern int ar531x_find_config(char *flash_limit);
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extern void ar5312_prom_init(void);
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extern void ar5312_misc_intr_init(int irq_base);
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extern void ar5312_plat_setup(void);
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extern asmlinkage void ar5312_irq_dispatch(void);
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extern void ar5315_prom_init(void);
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extern void ar5315_misc_intr_init(int irq_base);
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extern void ar5315_plat_setup(void);
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extern asmlinkage void ar5315_irq_dispatch(void);
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extern void ar5315_pci_irq(int irq);
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static inline u32 sysRegMask(u32 phys, u32 mask, u32 value)
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{
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u32 reg;
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reg = sysRegRead(phys);
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reg &= ~mask;
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reg |= value & mask;
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sysRegWrite(phys, reg);
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reg = sysRegRead(phys); /* flush write to the hardware */
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return reg;
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}
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#endif
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